Displaying 11 results from an estimated 11 matches for "gr32_nosp".
2017 Jul 28
3
Purpose of various register classes in X86 target
Hello Matthias,
On 28 July 2017 at 04:13, Matthias Braun <mbraun at apple.com> wrote:
> It's not that hard in principle:
> - A register class is a set of registers.
> - Virtual Registers have a register class assigned.
> - If you have register constraints (like x86 8bit operations only work on
> al,ah,etc.) then you have to create a new register class to express that.
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...OpNum].isOptionalDef();
> // If the instruction requires a register in a different class, create
> // a new virtual register and copy the value into it, but first attempt to
> // shrink VReg's register class within reason. For example, if VReg == GR32
> // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
> if (II) {
> const TargetRegisterClass *DstRC = nullptr;
> if (IIOpNum < II->getNumOperands())
> DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
> if (DstRC && !MRI->constrainRegCl...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...// If the instruction requires a register in a different class, create
>> // a new virtual register and copy the value into it, but first attempt
>> to
>> // shrink VReg's register class within reason. For example, if VReg ==
>> GR32
>> // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
>> if (II) {
>> const TargetRegisterClass *DstRC = nullptr;
>> if (IIOpNum < II->getNumOperands())
>> DstRC =
>> TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
>> if (DstRC &...
2015 Aug 25
4
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...lDef();
>> // If the instruction requires a register in a different class, create
>> // a new virtual register and copy the value into it, but first attempt to
>> // shrink VReg's register class within reason. For example, if VReg == GR32
>> // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
>> if (II) {
>> const TargetRegisterClass *DstRC = nullptr;
>> if (IIOpNum < II->getNumOperands())
>> DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
>> if (DstRC && !MR...
2011 Jun 15
0
[LLVMdev] Custom allocation orders
...nce (sub GR8, AH, BH, CH, DH), there is no need the repeat the entire register list. TableGen can also verify that the alternative allocation orders don't include foreign registers. That would be illegal.
Finally, suppose TableGen wanted to create a register class with the GR8 sub-registers of GR32_NOSP. It would be able to automatically create an allocation order for such a class by basing it on the GR8 order.
I will make this change soon. Out-of-tree targets will need to change their .td files, but most likely they can simply delete the custom allocation orders entirely. That was the case for...
2015 Aug 24
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
> On Aug 24, 2015, at 1:30 PM, Ryan Taylor <ryta1203 at gmail.com> wrote:
>
> I'm trying to do something like this:
>
> // Dst = NewVReg's reg class
> // *II = MCInstrDesc
> // IIOpNum = II Operand Num
>
> if (TRI->getCommonSubClass(DstRC, TRI->getRegClass(II->OpInfo[IIOpNum].RegClass)) == DstRC)
> MRI->setRegClass(VReg, DstRC);
>
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...// a new virtual register and copy the value into it, but first
>>>>>>> attempt to
>>>>>>> // shrink VReg's register class within reason. For example, if
>>>>>>> VReg == GR32
>>>>>>> // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
>>>>>>> if (II) {
>>>>>>> const TargetRegisterClass *DstRC = nullptr;
>>>>>>> if (IIOpNum < II->getNumOperands())
>>>>>>> DstRC =
>>>>>>>...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...ual register and copy the value into it, but first
>>>>>>>> attempt to
>>>>>>>> // shrink VReg's register class within reason. For example, if
>>>>>>>> VReg == GR32
>>>>>>>> // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
>>>>>>>> if (II) {
>>>>>>>> const TargetRegisterClass *DstRC = nullptr;
>>>>>>>> if (IIOpNum < II->getNumOperands())
>>>>>>>> DstRC =
>>>...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...copy the value into it, but first
>>>>>>>>> attempt to
>>>>>>>>> // shrink VReg's register class within reason. For example, if
>>>>>>>>> VReg == GR32
>>>>>>>>> // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
>>>>>>>>> if (II) {
>>>>>>>>> const TargetRegisterClass *DstRC = nullptr;
>>>>>>>>> if (IIOpNum < II->getNumOperands())
>>>>>>>>> DstR...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...into it, but first
>>>>>>>>>> attempt to
>>>>>>>>>> // shrink VReg's register class within reason. For example, if
>>>>>>>>>> VReg == GR32
>>>>>>>>>> // and II requires a GR32_NOSP, just constrain VReg to
>>>>>>>>>> GR32_NOSP.
>>>>>>>>>> if (II) {
>>>>>>>>>> const TargetRegisterClass *DstRC = nullptr;
>>>>>>>>>> if (IIOpNum < II->getNumOperan...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...;>>>>>>>>>> first attempt to
>>>>>>>>>>> // shrink VReg's register class within reason. For example,
>>>>>>>>>>> if VReg == GR32
>>>>>>>>>>> // and II requires a GR32_NOSP, just constrain VReg to
>>>>>>>>>>> GR32_NOSP.
>>>>>>>>>>> if (II) {
>>>>>>>>>>> const TargetRegisterClass *DstRC = nullptr;
>>>>>>>>>>> if (IIOpNum < II-...