Displaying 7 results from an estimated 7 matches for "gr32_abcd".
2013 Mar 21
9
[LLVMdev] Simpler types in TableGen isel patterns
...1 and $src2 from the specified register classes, and that is the only purpose of the register classes in a pattern like that. SelectionDAG doesn't really understand register classes, it only uses types.
If I try to constrain the register class in a pattern, like this:
def : Pat<(and (not GR32_ABCD:$src1), GR32_ABCD:$src2),
(ANDN32rr GR32_ABCD:$src1, GR32_ABCD:$src2)>;
I get completely ignored. SelectionDAG's InstrEmitter will still use the GR32 register class that was assigned to the i32 type.
When using register classes as proxies for types, it also becomes very difficu...
2013 Mar 21
0
[LLVMdev] Simpler types in TableGen isel patterns
...register classes, and that is the only purpose of the register
> classes in a pattern like that. SelectionDAG doesn't really
> understand register classes, it only uses types.
>
> If I try to constrain the register class in a pattern, like this:
>
> def : Pat<(and (not GR32_ABCD:$src1), GR32_ABCD:$src2),
> (ANDN32rr GR32_ABCD:$src1, GR32_ABCD:$src2)>;
>
> I get completely ignored. SelectionDAG's InstrEmitter will still use
> the GR32 register class that was assigned to the i32 type.
>
> When using register classes as proxies for types...
2013 Mar 23
0
[LLVMdev] Simpler types in TableGen isel patterns
...gister
> classes, and that is the only purpose of the register classes in a pattern
> like that. SelectionDAG doesn't really understand register classes, it only
> uses types.
>
> If I try to constrain the register class in a pattern, like this:
>
> def : Pat<(and (not GR32_ABCD:$src1), GR32_ABCD:$src2),
> (ANDN32rr GR32_ABCD:$src1, GR32_ABCD:$src2)>;
>
> I get completely ignored. SelectionDAG's InstrEmitter will still use the
> GR32 register class that was assigned to the i32 type.
>
> When using register classes as proxies for types,...
2013 Mar 21
1
[LLVMdev] Simpler types in TableGen isel patterns
...is the only purpose of the register
> > classes in a pattern like that. SelectionDAG doesn't really
> > understand register classes, it only uses types.
> >
> > If I try to constrain the register class in a pattern, like this:
> >
> > def : Pat<(and (not GR32_ABCD:$src1), GR32_ABCD:$src2),
> > (ANDN32rr GR32_ABCD:$src1, GR32_ABCD:$src2)>;
> >
> > I get completely ignored. SelectionDAG's InstrEmitter will still use
> > the GR32 register class that was assigned to the i32 type.
> >
> > When using register...
2013 Mar 21
0
[LLVMdev] Simpler types in TableGen isel patterns
...gister
> classes, and that is the only purpose of the register classes in a pattern
> like that. SelectionDAG doesn't really understand register classes, it only
> uses types.
>
> If I try to constrain the register class in a pattern, like this:
>
> def : Pat<(and (not GR32_ABCD:$src1), GR32_ABCD:$src2),
> (ANDN32rr GR32_ABCD:$src1, GR32_ABCD:$src2)>;
>
> I get completely ignored. SelectionDAG's InstrEmitter will still use the
> GR32 register class that was assigned to the i32 type.
>
> When using register classes as proxies for types,...
2010 Jun 16
0
[LLVMdev] Simpler subreg ops in machine code IR
On Jun 15, 2010, at 2:48 PM, Jakob Stoklund Olesen wrote:
> I am considering adding a new target independent codegen-only COPY instruction to our MachineInstr representation. It would be used to replace INSERT_SUBREG, EXTRACT_SUBREG, and virtual register copies after instruction selection. Selection DAG still needs {INSERT,EXTRACT}_SUBREG, but they would not appear as MachineInstrs any longer.
2010 Jun 15
4
[LLVMdev] Simpler subreg ops in machine code IR
I am considering adding a new target independent codegen-only COPY instruction to our MachineInstr representation. It would be used to replace INSERT_SUBREG, EXTRACT_SUBREG, and virtual register copies after instruction selection. Selection DAG still needs {INSERT,EXTRACT}_SUBREG, but they would not appear as MachineInstrs any longer.
The COPY instruction handles subreg operations with less