search for: gprregclass

Does anyone understand the purpose of this target inpdendent function? By adding a new register class that is for MIPS16 but not even referencing it, the compiler breaks because of this code. def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add // Return Values and Arguments V0, V1, A0, A1, A2, A3, // Callee save S0, S1 )>; I'm trying to understand how the

Does anyone understand the purpose of : TargetRegisterInfo::getMinimalPhysRegClass ??? Why is there the presumption to use the minimal subclass? For Mips, it would work for me if we changed this to a virtual function and then I could override this to have it chose the proper register class based on the processor. I want to introduct a different register class for MIPS 16 but don't want

I've been experimenting with llvm/clang as a user for a while now, but now I'm interested in writing my own backend. I'm also developing the target architecture (maybe to go in an fpga eventually) and I'm intentionally making it extremely simple. I think of it as a narrow microcode, because (for example) performing an add requires a sequence of instructions like: set aluin1 = r1

...) const { - AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) - .addReg(SrcReg, getKillRegState(KillSrc))); + // Need to check the arch. + MachineFunction &MF = *MBB.getParent(); + const ARMSubtarget &st = MF.getTarget().getSubtarget<ARMSubtarget>(); + assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && "Thumb1 can only copy GPR registers"); + + if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg) + || ! ARM::tGPRRegClass.contains(DestReg)) { + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) + .addReg(SrcReg, ge...