search for: gprr1

...;re normal allocatable registers, you may be able to define a register class containing only the fixed register then defining the instruction(s) using those as operands. Something like, for a 32-bit register for target FOO: def GPRr0 : RegisterClass<"FOO", [i32], 32, (add R0)>; def GPRr1 : RegisterClass<"FOO", [i32], 32, (add R1)>; def GPRr2 : RegisterClass<"FOO", [i32], 32, (add R2)>; The an instruction that uses R0 and R1 as fixed input registers and R2 for output could define itself using those register classs: def myInst : baseclass<…, (outs...

Jim, > The an instruction that uses R0 and R1 as fixed input registers and R2 for output could define itself using those register classs: > def myInst : baseclass<…, (outs GPRr2:$dst), (ins GPRr0:$src1, GPRr1:$src2), …> > Use those reg classes in pattern to match also, and things should just work. The register allocator can take care of any reg-to-reg copies that are required. As far as I understand Jonas, this does not work in his case... -- With best regards, Anton Korobeynikov Faculty of Math...

Hi, I have som instructions that require the operand to be placed in exactly one physical register, and thus I have introduced a Just_a0 register class. I have found that the register allocators / coalescer do not seem to care about this. In many cases they "run out of registers during register allocation". I have managed to avoid some problems, by inserting target move instructions in

Hello Jonas, > I wonder, what would be the best solution for instructions that require > operands in a particular register, and even gives the result in a particular > register? You need to custom select such instruction. See e.g. div / idiv on x86 as an example. -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University