Displaying 2 results from an estimated 2 matches for "gprr".
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gpr
2012 May 09
0
[LLVMdev] instructions requiring specific physical registers for operands
Jim,
> The an instruction that uses R0 and R1 as fixed input registers and R2 for output could define itself using those register classs:
> def myInst : baseclass<…, (outs GPRr2:$dst), (ins GPRr0:$src1, GPRr1:$src2), …>
> Use those reg classes in pattern to match also, and things should just work. The register allocator can take care of any reg-to-reg copies that are required.
As far as I understand Jonas, this does not work in his case...
--
With best regards, An...
2012 May 09
2
[LLVMdev] instructions requiring specific physical registers for operands
...gt; as an example.
That's often easiest, yes; however, if they're normal allocatable registers, you may be able to define a register class containing only the fixed register then defining the instruction(s) using those as operands.
Something like, for a 32-bit register for target FOO:
def GPRr0 : RegisterClass<"FOO", [i32], 32, (add R0)>;
def GPRr1 : RegisterClass<"FOO", [i32], 32, (add R1)>;
def GPRr2 : RegisterClass<"FOO", [i32], 32, (add R2)>;
The an instruction that uses R0 and R1 as fixed input registers and R2 for output could define...