search for: gprnopc

..., (i32 31)), GPR:$RdHi, CPSR)))] This results in 'expected identifier in dag init' error. Obviously something is wrong in this pattern, I have not figured out what that is ? 2) ldrb r2, [r2] ldrb r3, [r3] smlal r0, r1, r3, r2 ==> smlalbb r0, r1, r3, r2 def : ARMV5MOPat<(smlal GPRnopc:$RdLo, GPRnopc:$RdHi, (sra (shl GPR:$a, (i32 24)), (i32 24)), (sra (shl GPR:$b, (i32 24)), (i32 24))), (SMLALBB GPRnopc:$RdLo, GPRnopc:$RdHi, GPRnopc:$Rn, GPRnopc:Rm)>; This throws "Variable not defined: 'smlal'...

...%noreg %r0 = LDRi12 %stack.2, 14, %noreg %r0 = SUBri %r0, 1, 14, %noreg, %noreg CMPri %r0, 3, 14, %noreg, implicit-def %cpsr STRi12 %r0, %stack.3, 14, %noreg Bcc %bb.6, 8, %cpsr Successors according to CFG: %bb.6 %bb.1 %bb.1: derived from LLVM BB %1 Predecessors according to CFG: %bb.0 %1:gprnopc = LEApcrelJT %jump-table.0, 14, %noreg %2:gprnopc = LDRrs killed %0:gprnopc, %1, 0, 14, %noreg; mem:LD4[JumpTable] BR_JTr killed %2, %jump-table.0 Successors according to CFG: %bb.2(?%) %bb.3(?%) %bb.4(?%) %bb.5(?%) %bb.2: derived from LLVM BB %2 Predecessors according to CFG: %bb.1 %r0 =...

...0 = LDRi12 %stack.2, 14, %noreg %r0 = SUBri %r0, 1, 14, %noreg, %noreg CMPri %r0, 3, 14, %noreg, implicit-def %cpsr STRi12 %r0, %stack.3, 14, %noreg Bcc %bb.6, 8, %cpsr Successors according to CFG: %bb.6 %bb.1 %bb.1: derived from LLVM BB %1 Predecessors according to CFG: %bb.0 %1:gprnopc = LEApcrelJT %jump-table.0, 14, %noreg %2:gprnopc = LDRrs killed %0:gprnopc, %1, 0, 14, %noreg; mem:LD4[JumpTable] BR_JTr killed %2, %jump-table.0 Successors according to CFG: %bb.2(?%) %bb.3(?%) %bb.4(?%) %bb.5(?%) %bb.2: derived from LLVM BB %2 Predecessors according to CFG: %bb.1...

...0 = LDRi12 %stack.2, 14, %noreg %r0 = SUBri %r0, 1, 14, %noreg, %noreg CMPri %r0, 3, 14, %noreg, implicit-def %cpsr STRi12 %r0, %stack.3, 14, %noreg Bcc %bb.6, 8, %cpsr Successors according to CFG: %bb.6 %bb.1 %bb.1: derived from LLVM BB %1 Predecessors according to CFG: %bb.0 %1:gprnopc = LEApcrelJT %jump-table.0, 14, %noreg %2:gprnopc = LDRrs killed %0:gprnopc, %1, 0, 14, %noreg; mem:LD4[JumpTable] BR_JTr killed %2, %jump-table.0 Successors according to CFG: %bb.2(?%) %bb.3(?%) %bb.4(?%) %bb.5(?%) %bb.2: derived from LLVM BB %2 Predecessors according to CFG: %bb.1...

...%noreg %r0 = LDRi12 %stack.2, 14, %noreg %r0 = SUBri %r0, 1, 14, %noreg, %noreg CMPri %r0, 3, 14, %noreg, implicit-def %cpsr STRi12 %r0, %stack.3, 14, %noreg Bcc %bb.6, 8, %cpsr Successors according to CFG: %bb.6 %bb.1 %bb.1: derived from LLVM BB %1 Predecessors according to CFG: %bb.0 %1:gprnopc = LEApcrelJT %jump-table.0, 14, %noreg %2:gprnopc = LDRrs killed %0:gprnopc, %1, 0, 14, %noreg; mem:LD4[JumpTable] BR_JTr killed %2, %jump-table.0 Successors according to CFG: %bb.2(?%) %bb.3(?%) %bb.4(?%) %bb.5(?%) %bb.2: derived from LLVM BB %2 Predecessors according to CFG: %bb.1 %r0 =...

Is there a way in tablegen to specify that a certain instruction can only be allocated with a certain subset of a register class? Thanks, Micah -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20110816/329bea6e/attachment.html>

Hi Micah, You can just create a new register class that only contains the registers you want and use that for the instruction. The set theoretic operators for register class definition make this very easy. See the ARM backend definitions of GPRnopc, rGPR, etc.. for examples. -Jim On Aug 16, 2011, at 9:18 AM, Villmow, Micah wrote: > Is there a way in tablegen to specify that a certain instruction can only be allocated with a certain subset of a register class? > > Thanks, > Micah > __________________________________________...

...set of > registers > > Hi Micah, > > You can just create a new register class that only contains the > registers you want and use that for the instruction. The set theoretic > operators for register class definition make this very easy. See the > ARM backend definitions of GPRnopc, rGPR, etc.. for examples. > > -Jim > > On Aug 16, 2011, at 9:18 AM, Villmow, Micah wrote: > > > Is there a way in tablegen to specify that a certain instruction can > only be allocated with a certain subset of a register class? > > > > Thanks, > > Micah...

...trInfo that it inherited from ARMBaseInstrInfo with the "patched" one. (This "patching", still, happens at compile-time.) As John rightly noted, this approach looks rather hacky and confusing: This isn't "rGPR includes SP" it's "rGPR is #defined to GPRnopc", which makes things really confusing if you're just looking at the .td files to figure out what's what you see instructions that use rGPR, and you see a definition of the rGPR register class, but those instructions may actually be redefined to use GPRnopc due to something happening e...

...ed when doing this. It seems kind of cumbersome to add 4-5 custom decoder methods and I'm concerned about the post-encode method because this didn't seem to be causing codegen issues before, and I haven't had time to test this yet. The cleaner solution would seem to have been to put GPRnopc register constraints on the tablegen stuff for the index in other variants, but these are ignored during decoding / disassembly. Is there anyone more familiar with Tablegen who might be able to point out a cleaner way of fixing this issue? I don't have the patch files on my home computer but...