Displaying 8 results from an estimated 8 matches for "gpri64".
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gpr64
2008 Oct 30
0
[LLVMdev] Using patterns inside patterns
I am not sure what you are looking to do. Please provide a mark up
example.
Evan
On Oct 28, 2008, at 11:00 AM, Villmow, Micah wrote:
> Is there currently a way to use a pattern inside of another pattern?
>
> Micah Villmow
> Systems Engineer
> Advanced Technology & Performance
> Advanced Micro Devices Inc.
> 4555 Great America Pkwy,
> Santa Clara, CA. 95054
> P:
2008 Oct 30
1
[LLVMdev] Using patterns inside patterns
...er, so I have this pattern:
// integer subtraction
// a - b ==> a + (-b)
def ISUB : Pat<(sub GPRI32:$src0, GPRI32:$src1),
(IADD GPRI32:$src0, (INEGATE GPRI32:$src1))>;
I am attemping to do 64 bit integer shifts and using the following
pattern:
def LSHL : Pat<(shl GPRI64:$src0, GPRI32:$src1),
(LCREATE (ISHL (LLO GPRI64:$src0), GPRI32:$src1),
(IOR (ISHL (LHI GPRI64:$src0), GPRI32:$src1), (IOR (USHR (LLO
GPRI64:$src0), (IADD (LOADCONST_i32 32), (INEGATE GPRI32:$src1))), (USHR
(LLO GPRI64:$src0), (IADD GPRI32:$src1, (LOADCONST_i32 -32))))))>;...
2008 Oct 28
4
[LLVMdev] Using patterns inside patterns
Is there currently a way to use a pattern inside of another pattern?
Micah Villmow
Systems Engineer
Advanced Technology & Performance
Advanced Micro Devices Inc.
4555 Great America Pkwy,
Santa Clara, CA. 95054
P: 408-572-6219
F: 408-572-6596
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2012 Apr 19
2
[LLVMdev] Tablegen to match a literal in an instruction
...nt<ILOpCode OpCode, SDNode OpNode> {
def _i8 : BinaryOp<OpCode, OpNode, GPRI8, GPRI8, GPRI8>;
def _i16 : BinaryOp<OpCode, OpNode, GPRI16, GPRI16, GPRI16>;
def _i32 : BinaryOp<OpCode, OpNode, GPRI32, GPRI32, GPRI32>;
def _i64 : BinaryOp<OpCode, OpNode, GPRI64, GPRI64, GPRI64>;
}
defm AND : BinaryOpMCInt<IL_OP_AND, and>;
I want to turn this into a register/immediate pattern by changing it to:
class ILFormat<dag outs, dag ins, string asmstr, list<dag> pattern>
: Instruction {
let Namespace = "AMDIL";
dag Ou...
2012 Apr 19
3
[LLVMdev] Tablegen to match a literal in an instruction
...nt<ILOpCode OpCode, SDNode OpNode> {
def _i8 : BinaryOp<OpCode, OpNode, GPRI8, GPRI8, GPRI8>;
def _i16 : BinaryOp<OpCode, OpNode, GPRI16, GPRI16, GPRI16>;
def _i32 : BinaryOp<OpCode, OpNode, GPRI32, GPRI32, GPRI32>;
def _i64 : BinaryOp<OpCode, OpNode, GPRI64, GPRI64, GPRI64>;
}
defm AND : BinaryOpMCInt<IL_OP_AND, and>;
I want to turn this into a register/immediate pattern by changing it to:
class ILFormat<dag outs, dag ins, string asmstr, list<dag> pattern>
: Instruction {
let Namespace = "AMDIL";
dag Ou...
2012 Apr 19
0
[LLVMdev] Tablegen to match a literal in an instruction
...ode OpNode> {
> def _i8 : BinaryOp<OpCode, OpNode, GPRI8, GPRI8, GPRI8>;
>
> def _i16 : BinaryOp<OpCode, OpNode, GPRI16, GPRI16, GPRI16>;
> def _i32 : BinaryOp<OpCode, OpNode, GPRI32, GPRI32, GPRI32>;
> def _i64 : BinaryOp<OpCode, OpNode, GPRI64, GPRI64, GPRI64>;
> }
> defm AND : BinaryOpMCInt<IL_OP_AND, and>;
>
> I want to turn this into a register/immediate pattern by changing it to:
> class ILFormat<dag outs, dag ins, string asmstr, list<dag> pattern>
> : Instruction {
> let Namesp...
2012 Apr 19
0
[LLVMdev] Tablegen to match a literal in an instruction
...ode OpNode> {
> def _i8 : BinaryOp<OpCode, OpNode, GPRI8, GPRI8, GPRI8>;
>
> def _i16 : BinaryOp<OpCode, OpNode, GPRI16, GPRI16, GPRI16>;
> def _i32 : BinaryOp<OpCode, OpNode, GPRI32, GPRI32, GPRI32>;
> def _i64 : BinaryOp<OpCode, OpNode, GPRI64, GPRI64, GPRI64>;
> }
> defm AND : BinaryOpMCInt<IL_OP_AND, and>;
>
> I want to turn this into a register/immediate pattern by changing it to:
> class ILFormat<dag outs, dag ins, string asmstr, list<dag> pattern>
> : Instruction {
> let Namesp...
2008 Nov 18
1
[LLVMdev] 32 bit boolean results
You can tell LLVM that you have "sign extended" setCC results (all
ones).
Dan
On Nov 18, 2008, at 5:33 PM, Eli Friedman wrote:
> On Tue, Nov 18, 2008 at 1:56 PM, Villmow, Micah
> <Micah.Villmow at amd.com> wrote:
>> The IR produces correct results, but my backend does not and the
>> only thing
>> I can think of is that the IR is treating the