Displaying 4 results from an estimated 4 matches for "gpri16".
2012 Apr 19
2
[LLVMdev] Tablegen to match a literal in an instruction
...!strconcat(op.Text, " $dst, $src0, $src1"),
[(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>;
multiclass BinaryOpMCInt<ILOpCode OpCode, SDNode OpNode> {
def _i8 : BinaryOp<OpCode, OpNode, GPRI8, GPRI8, GPRI8>;
def _i16 : BinaryOp<OpCode, OpNode, GPRI16, GPRI16, GPRI16>;
def _i32 : BinaryOp<OpCode, OpNode, GPRI32, GPRI32, GPRI32>;
def _i64 : BinaryOp<OpCode, OpNode, GPRI64, GPRI64, GPRI64>;
}
defm AND : BinaryOpMCInt<IL_OP_AND, and>;
I want to turn this into a register/immediate pattern by changing it to:
cla...
2012 Apr 19
3
[LLVMdev] Tablegen to match a literal in an instruction
...!strconcat(op.Text, " $dst, $src0, $src1"),
[(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>;
multiclass BinaryOpMCInt<ILOpCode OpCode, SDNode OpNode> {
def _i8 : BinaryOp<OpCode, OpNode, GPRI8, GPRI8, GPRI8>;
def _i16 : BinaryOp<OpCode, OpNode, GPRI16, GPRI16, GPRI16>;
def _i32 : BinaryOp<OpCode, OpNode, GPRI32, GPRI32, GPRI32>;
def _i64 : BinaryOp<OpCode, OpNode, GPRI64, GPRI64, GPRI64>;
}
defm AND : BinaryOpMCInt<IL_OP_AND, and>;
I want to turn this into a register/immediate pattern by changing it to:
cla...
2012 Apr 19
0
[LLVMdev] Tablegen to match a literal in an instruction
...uot; $dst, $src0, $src1"),
> [(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>;
> multiclass BinaryOpMCInt<ILOpCode OpCode, SDNode OpNode> {
> def _i8 : BinaryOp<OpCode, OpNode, GPRI8, GPRI8, GPRI8>;
>
> def _i16 : BinaryOp<OpCode, OpNode, GPRI16, GPRI16, GPRI16>;
> def _i32 : BinaryOp<OpCode, OpNode, GPRI32, GPRI32, GPRI32>;
> def _i64 : BinaryOp<OpCode, OpNode, GPRI64, GPRI64, GPRI64>;
> }
> defm AND : BinaryOpMCInt<IL_OP_AND, and>;
>
> I want to turn this into a register/immediate...
2012 Apr 19
0
[LLVMdev] Tablegen to match a literal in an instruction
...uot; $dst, $src0, $src1"),
> [(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>;
> multiclass BinaryOpMCInt<ILOpCode OpCode, SDNode OpNode> {
> def _i8 : BinaryOp<OpCode, OpNode, GPRI8, GPRI8, GPRI8>;
>
> def _i16 : BinaryOp<OpCode, OpNode, GPRI16, GPRI16, GPRI16>;
> def _i32 : BinaryOp<OpCode, OpNode, GPRI32, GPRI32, GPRI32>;
> def _i64 : BinaryOp<OpCode, OpNode, GPRI64, GPRI64, GPRI64>;
> }
> defm AND : BinaryOpMCInt<IL_OP_AND, and>;
>
> I want to turn this into a register/immediate...