Displaying 7 results from an estimated 7 matches for "gprclass".
2007 Feb 14
2
[LLVMdev] Linux/ppc backend
...CR0,CR1,CR5,CR6,CR7}
static const unsigned Defs_Macho[] =
{R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
LR,CTR,
CR0,CR1,CR5,CR6,CR7}
GPRClass::iterator
GPRClass::allocation_order_begin(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const PPCSubtarget &Subtarget = TM.getSubtarget<PPCSubtarget>();
if (Subtarget.isMachoABI()){
return Defs_Macho;
} else {...
2007 Feb 15
0
[LLVMdev] Linux/ppc backend
...static const unsigned Defs_Macho[] =
> {R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
> F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
>
> V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
> LR,CTR,
> CR0,CR1,CR5,CR6,CR7}
>
> GPRClass::iterator
> GPRClass::allocation_order_begin(const MachineFunction &MF)
> const {
> const TargetMachine &TM = MF.getTarget();
> const PPCSubtarget &Subtarget = TM.getSubtarget<PPCSubtarget>();
> if (Subtarget.isMachoABI()){
> retur...
2007 Feb 02
0
[LLVMdev] Linux/ppc backend
On Fri, 2 Feb 2007, Nicolas Geoffray wrote:
> I have almost completed the implementation of a linux/ppc backend in llvm.
Cool!
> There were a few things to modify in
> lib/Target/PowerPC with a lot of "if (!isDarwin)".
Some meta comments:
1. Please don't change PPC -> llvmPPC. I assume that you did this because
PPC is a #define in some system header. Please
2007 Feb 02
5
[LLVMdev] Linux/ppc backend
Hi everyone,
I have almost completed the implementation of a linux/ppc backend in
llvm. There were a few things to modify in
lib/Target/PowerPC with a lot of "if (!isDarwin)".
There are some places where I need help before saying the port is
complete. I attached the diff file as a reference
1) In order to generate a creqv instruction before a vararg call, I
created a new
2010 Jan 04
5
[LLVMdev] How to bind a register variable with a given general purpose register?
Hi everyone,
There are 16 GPRs in my RISC, but in fact GPR13 is read-only and connected
to output of an A/D converter.
It would be very convenient if i could bind a register variable with GPR13.
Because i am a newbie i don't know how my llvm backend can support that.
I plan to implement it as below.
A. first declare a global variable in c-code
int ADC asm("GPR13");
B. If
2010 Jan 04
0
[LLVMdev] 答复: [LLVMdev] How to bind a register variable with a given general purpose register?
...(GPR13));"
2. add a intrinsic functions like "llvm.zhu.readadcreg()".
3. map any read to the variable marked with __attribute__((GPR13)) to
llvm.zhu.readadcreg() instead of "load" instruction
4. assign gpr13 to a special register class like "gpr13class" instead of
gprclass, so gpr13 will not be allocated as other gpr.
5. lower instrinisic functions "llvm.zhu.readadcreg()" to register node
"gpr13" in your backend.
regards
--ether
On 2010-1-4 18:01, Demon(Xiangyang) Zhu 朱向阳 wrote:
> Hi Ether,
>
> The hardware had been fixed now.
> If...
2010 Jan 04
0
[LLVMdev] 答复: 答复: [LLVMdev] How to bind a register variable with a given general purpose register?
...dd a intrinsic functions like "llvm.zhu.readadcreg()".
> 3. map any read to the variable marked with __attribute__((GPR13)) to
> llvm.zhu.readadcreg() instead of "load" instruction
> 4. assign gpr13 to a special register class like "gpr13class" instead of
> gprclass, so gpr13 will not be allocated as other gpr.
> 5. lower instrinisic functions "llvm.zhu.readadcreg()" to register node
> "gpr13" in your backend.
>
> regards
>
> --ether
>
> On 2010-1-4 18:01, Demon(Xiangyang) Zhu 朱向阳 wrote:
>
>> Hi Ether,
&g...