Displaying 6 results from an estimated 6 matches for "gprbasereg".
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gprbaseregs
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
1. MOV16Copy_IMM_REG is the instruction matched, sorry. AD is the
multiclass. The IMM in my case is a global. So you can see that
GPRBaseRegs, GPRBaseRegs sets the registerclass for both the src and dst
operands, in this case (MOV16Copy_IMM_REG) it's the dst.
2. Yes I agree, it most likely would.
Honestly, this comes across like a bug, or unintended feature. It's adding
an extra COPY to move from a GPR to a Base when a Base is...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...that it suddenly just changed behavior.
It looks like to me that InstrEmitter.cpp:getVR is the one assigning the
virtual register no?
Though this code in CreateVirtualRegisters:
const TargetRegisterClass *RC =
TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
That returns GPRBaseRegs for RC, but it then decides to constrain it based
on type:
if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
const TargetRegisterClass *VTRC =
TLI->getRegClassFor(Node->getSimpleValueType(i));
errs()<<"CVR VTRC: "<...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...IRC getVR only create the virtual register for implicit defs. Which
> is not your case, right?
>
>
> Though this code in CreateVirtualRegisters:
>
> const TargetRegisterClass *RC =
> TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
>
> That returns GPRBaseRegs for RC, but it then decides to constrain it based
> on type:
>
> if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
> const TargetRegisterClass *VTRC =
> TLI->getRegClassFor(Node->getSimpleValueType(i));
> errs()<...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...[(directStore (dstType (OpNode
srcAReg:$srcA)), addr16:$dstD)]>;
def MEM_MEM : SetADIn<asmstr, memhx, memhx,
[(directStore (dstType (OpNode (srcAType
(load addr16:$srcA)))), addr16:$dstD)]>;
}
defm MOV16Copy_ : AD<"mov16", null_frag, GPRBaseRegs, GPRBaseRegs,
i16, i16, simm16, immSExt16x>;
On Tue, Aug 25, 2015 at 1:02 PM, Ryan Taylor <ryta1203 at gmail.com> wrote:
> Quentin,
>
> 1. I'll take a look, it's also picking the reg class by the
> SimpleValueType and then getting the common subclass. Choosing to c...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...gister for implicit defs. Which
>> is not your case, right?
>>
>>
>> Though this code in CreateVirtualRegisters:
>>
>> const TargetRegisterClass *RC =
>> TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
>>
>> That returns GPRBaseRegs for RC, but it then decides to constrain it
>> based on type:
>>
>> if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
>> const TargetRegisterClass *VTRC =
>> TLI->getRegClassFor(Node->getSimpleValueType(i));
&...
2015 Aug 25
4
[LLVMdev] TableGen Register Class not matching for MI in 3.6
Hi Ryan,
> On Aug 24, 2015, at 6:49 PM, Ryan Taylor <ryta1203 at gmail.com> wrote:
>
> Quentin,
>
> I apologize for the spamming here but in getVR (where VReg is assigned an RC), it calls:
>
> const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getSimpleValueType());
> VReg = MRI->createVirtualRegister(RC);
>
> My question is why is it using the