search for: gprbase

...[(directStore (dstType (OpNode srcAReg:$srcA)), addr16:$dstD)]>; def MEM_MEM : SetADIn<asmstr, memhx, memhx, [(directStore (dstType (OpNode (srcAType (load addr16:$srcA)))), addr16:$dstD)]>; } defm MOV16Copy_ : AD<"mov16", null_frag, GPRBaseRegs, GPRBaseRegs, i16, i16, simm16, immSExt16x>; On Tue, Aug 25, 2015 at 1:02 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > Quentin, > > 1. I'll take a look, it's also picking the reg class by the > SimpleValueType and then getting the common subclass. Choosing t...

1. MOV16Copy_IMM_REG is the instruction matched, sorry. AD is the multiclass. The IMM in my case is a global. So you can see that GPRBaseRegs, GPRBaseRegs sets the registerclass for both the src and dst operands, in this case (MOV16Copy_IMM_REG) it's the dst. 2. Yes I agree, it most likely would. Honestly, this comes across like a bug, or unintended feature. It's adding an extra COPY to move from a GPR to a Base when a Base...

...that it suddenly just changed behavior. It looks like to me that InstrEmitter.cpp:getVR is the one assigning the virtual register no? Though this code in CreateVirtualRegisters: const TargetRegisterClass *RC = TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); That returns GPRBaseRegs for RC, but it then decides to constrain it based on type: if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) { const TargetRegisterClass *VTRC = TLI->getRegClassFor(Node->getSimpleValueType(i)); errs()<<"CVR VTRC: "...

...escription of that mapping. I believe that we first create a VReg using that RC then constraint it with the RC in the td. Two things: 1. You can point me where you saw that and I can give you the exact meaning of the snippet. 2. You can change the mapping of your type in your RegisterInfo.td to map GPRBase instead of GPR and see if it does what you want. Cheers, -Quentin > > Thanks! > > On Mon, Aug 24, 2015 at 8:58 PM, Ryan Taylor <ryta1203 at gmail.com <mailto:ryta1203 at gmail.com>> wrote: > Quentin, > > This is the issue. Somewhere prior to the constrainRegCl...

...IRC getVR only create the virtual register for implicit defs. Which > is not your case, right? > > > Though this code in CreateVirtualRegisters: > > const TargetRegisterClass *RC = > TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); > > That returns GPRBaseRegs for RC, but it then decides to constrain it based > on type: > > if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) { > const TargetRegisterClass *VTRC = > TLI->getRegClassFor(Node->getSimpleValueType(i)); > errs()&...

...gister for implicit defs. Which >> is not your case, right? >> >> >> Though this code in CreateVirtualRegisters: >> >> const TargetRegisterClass *RC = >> TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); >> >> That returns GPRBaseRegs for RC, but it then decides to constrain it >> based on type: >> >> if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) { >> const TargetRegisterClass *VTRC = >> TLI->getRegClassFor(Node->getSimpleValueType(i))...

Quentin, This is the issue. Somewhere prior to the constrainRegClass, it's assigning the GPRBase sub class of GPR to the MOV instruction, so it can't constrain it to Base and hence has to add the COPY. Now I just need to find out why it is ignoring the TableGen defined GPRBase for the MOV MI in favor of it's sub class GPR. Thanks. On Mon, Aug 24, 2015 at 8:34 PM, Ryan Taylor <ryta...

> On Aug 24, 2015, at 4:46 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > Here is the snippet that matters: > > void > InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, > SDValue Op, > unsigned IIOpNum, > const MCInstrDesc *II, >