search for: gpr64opnd

Hi LLVM developers, GCC[1] is able to use Loongson ISA[2] for instruction selection: $ cat hello.c #include <stdio.h> int main(int argc, char *argv[]) { printf("Hello World\n"); return 0; } $ gcc -O0 -S hello.c $ cat hello.s .file 1 "hello.c" .section .mdebug.abi64 .previous .nan legacy .gnu_attribute 4, 1 .abicalls

...udoLowering.inc MipsGenAsmMatcher.inc I get an error. Included from /home/rkotler/workspace/llvm/lib/Target/Mips/MipsInstrInfo.td:1474: /home/rkotler/workspace/llvm/lib/Target/Mips/Mips64InstrInfo.td:89:1: error: Duplicate record in FastISel table! def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB, sub>, ADD_FM<0, 0x2e>; ^ make[3]: *** [/home/rkotler/llvmw/build/lib/Target/Mips/Debug+Asserts/MipsGenFastISel.inc.tmp] Error 1 Then it creates a blank file for MipsGenFastISel.inc and after that I get no build errors. I'm not sure what this is about . Any ideas?...

...e a > look at MipsInstrInfo.td file. In that file there are multiple > ISA_MIPSxxx classes. Take for example ISA_MIPS3 and search it through > *.td files. Here is an example of instruction definition specific to > mips3: > [[ > def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1, > bitconvert>, MFC1_FM<5>, ISA_MIPS3; > ]] > > More general and complete guide can be found here: > http://llvm.org/docs/WritingAnLLVMBackend.html <http://llvm.org/docs/WritingAnLLVMBackend.html> > > On Thu, Sep 6, 2018 at 1:01 PM Leslie...

I am trying to prototype a back end for a new processor. It has a 64-bit datapath, so all registers are 64 bits and load instructions always extend to 64 bits. But the type 'int' is 32 bits, and arithmetic instructions have variants that operate on only the lower 32 bits of each register. So for a basic 'a = b + c' example, we get %0 = load i32, i32* @b, align 4, !tbaa !1 %1