search for: gpr2

...set GPR:$dst, (fneg GPR:$src0))]>; With GPR defined as either an i32 or an f32. On another not, is there any known examples of using Tablegen with a typeless register class? Or with instruction formats where the modifiers are on the registers and the instructions(i.e. mul_x2 GPR0, GPR1_neg, GPR2_abs, which is equivalent to GPR0 = (-GPR1 * abs(GPR2)*2)? Thanks, Micah Villmow Systems Engineer Advanced Technology & Performance Advanced Micro Devices Inc. 4555 Great America Pkwy, Santa Clara, CA. 95054 P: 408-572-6219 F: 408-572-6596 -------------- next part ------------...

Hi Jakob, After reading your blog article, I have some questions. :-) In [1], it says: "It was an important design goal to make the algorithm as flexible as possible, and to avoid introducing arbitrary constraints. It is possible to change machine code and live ranges at any time. Simply evict the relevant live ranges, make the change, and put them back on the queue." Q1. The

...fe for our > purposes? > Quoting from a table titled Register Preservation on page 22 of this PDF: http://developer.apple.com/documentation/developertools/Conceptual/LowLevelABI/Mac_OS_X_ABI_Function_Call_Guide.pdf Reg Preserved Notes --------------------------- GPR0 No (No notes.) ... GPR2 No Available for general use. ... GPR11 Yes in nested functions. No in leaf functions. In nested functions, the caller passes its stackframe to the nested function in this register. In leaf functions, the register is available. For details on nested functions, see the GCC documentation. T...

...ion + .globl setjmp + .globl .setjmp +.setjmp: + mflr %r11 /* save return address */ + mfcr %r12 /* save condition register */ + mr %r10,%r1 /* save stack pointer */ + mr %r9,%r2 /* save GPR2 (not needed) */ + stmw %r9,0(%r3) /* save r9..r31 */ + li %r3,0 /* indicate success */ + blr /* return */ + + .size .setjmp,.-.setjmp + .section ".opd","aw" +longjmp: + .quad .longjmp,.TOC.@t...

...an i32 result, something is already messed up. > On another not, is there any known examples of using Tablegen with a > typeless register class? What do you mean? > Or with instruction formats where the modifiers are > on the registers and the instructions(i.e. mul_x2 GPR0, GPR1_neg, GPR2_abs, > which is equivalent to GPR0 = (-GPR1 * abs(GPR2)*2)? No examples I know of, but I don't think there should be any issues using multiclass, as long as there aren't too many possible modifiers; see http://llvm.org/docs/TableGenFundamentals.html and various uses in the code for how...

...mp: .globl setjmp .globl .setjmp .setjmp: - mflr %r11 /* save return address */ - mfcr %r12 /* save condition register */ - mr %r10,%r1 /* save stack pointer */ - mr %r9,%r2 /* save GPR2 (not needed) */ - stmw %r9,0(%r3) /* save r9..r31 */ - li %r3,0 /* indicate success */ - blr /* return */ + mflr %r11 /* save return address */ + mfcr %r12 /* save condition register */ + std %r2,0(%r3) /*...

...e setjmp, at function + .globl setjmp +setjmp: + mflr %r11 /* save return address */ + mfcr %r12 /* save condition register */ + mr %r10,%r1 /* save stack pointer */ + mr %r9,%r2 /* save GPR2 (not needed) */ + stmw %r9,0(%r3) /* save r9..r31 */ + li %r3,0 /* indicate success */ + blr /* return */ + + .size setjmp,.-setjmp + + .type longjmp, at function + .globl longjmp +longjmp: + lmw %r9,...

...is needed, then I just use 2 sequential 128bit registers. Also, my instruction set has basically unlimited registers, I can't really seem a way to model this either. > Or with instruction formats where the modifiers are > on the registers and the instructions(i.e. mul_x2 GPR0, GPR1_neg, GPR2_abs, > which is equivalent to GPR0 = (-GPR1 * abs(GPR2)*2)? No examples I know of, but I don't think there should be any issues using multiclass, as long as there aren't too many possible modifiers; see http://llvm.org/docs/TableGenFundamentals.html and various uses in the code for how...

...is needed, then I just use 2 sequential 128bit registers. Also, my instruction set has basically unlimited registers, I can't really seem a way to model this either. > Or with instruction formats where the modifiers are > on the registers and the instructions(i.e. mul_x2 GPR0, GPR1_neg, GPR2_abs, > which is equivalent to GPR0 = (-GPR1 * abs(GPR2)*2)? No examples I know of, but I don't think there should be any issues using multiclass, as long as there aren't too many possible modifiers; see http://llvm.org/docs/TableGenFundamentals.html and various uses in the code for how...

...8-0x000000000000042f SystemIO conflicts with Region \PMIO 1 (20120711/utaddress-251) [ 3.312689] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver [ 3.312692] ACPI Warning: 0x0000000000000500-0x000000000000053f SystemIO conflicts with Region \GPR2 1 (20120711/utaddress-251) [ 3.312695] ACPI Warning: 0x0000000000000500-0x000000000000053f SystemIO conflicts with Region \GPIO 2 (20120711/utaddress-251) [ 3.312698] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver [ 3.312699] lpc_ich: R...

I have updated the klibc patchset based on feedback received. In particular, the patchset has been reorganized so as not to break git-bisect. Additionally, this updates the patch base to 2.6.17-git12 (d38b69689c349f35502b92e20dafb30c62d49d63) and klibc 1.4.8; the main difference on the klibc side is removal of obsolete code. This is also available as a git tree at: