search for: gpcpll_coeff

...w) - 1) + +#define SYS_GPCPLL_CFG_BASE 0x00137000 +#define GPC_BCASE_GPCPLL_CFG_BASE 0x00132800 + +#define GPCPLL_CFG (SYS_GPCPLL_CFG_BASE + 0) +#define GPCPLL_CFG_ENABLE BIT(0) +#define GPCPLL_CFG_IDDQ BIT(1) +#define GPCPLL_CFG_LOCK_DET_OFF BIT(4) +#define GPCPLL_CFG_LOCK BIT(17) + +#define GPCPLL_COEFF (SYS_GPCPLL_CFG_BASE + 4) +#define GPCPLL_COEFF_M_SHIFT 0 +#define GPCPLL_COEFF_M_WIDTH 8 +#define GPCPLL_COEFF_N_SHIFT 8 +#define GPCPLL_COEFF_N_WIDTH 8 +#define GPCPLL_COEFF_P_SHIFT 16 +#define GPCPLL_COEFF_P_WIDTH 6 + +#define GPCPLL_CFG2 (SYS_GPCPLL_CFG_BASE + 0xc) +#define GPCPLL_CFG2_SETUP...

...137000 > +#define GPC_BCASE_GPCPLL_CFG_BASE 0x00132800 > + > +#define GPCPLL_CFG (SYS_GPCPLL_CFG_BASE + 0) > +#define GPCPLL_CFG_ENABLE BIT(0) > +#define GPCPLL_CFG_IDDQ BIT(1) > +#define GPCPLL_CFG_LOCK_DET_OFF BIT(4) > +#define GPCPLL_CFG_LOCK BIT(17) > + > +#define GPCPLL_COEFF (SYS_GPCPLL_CFG_BASE + 4) > +#define GPCPLL_COEFF_M_SHIFT 0 > +#define GPCPLL_COEFF_M_WIDTH 8 > +#define GPCPLL_COEFF_N_SHIFT 8 > +#define GPCPLL_COEFF_N_WIDTH 8 > +#define GPCPLL_COEFF_P_SHIFT 16 > +#define GPCPLL_COEFF_P_WIDTH 6 > + > +#define GPCPLL_CFG2 (SYS_GPCPLL_CF...

This series adds support for reclocking on GK20A. The first two patches touch the clock subsystem to allow GK20A to operate, by making the presence of the thermal and voltage devices optional, and allowing pstates to be provided directly instead of being probed using the BIOS (which Tegra does not have). The last patch adds the GK20A clock device. Arguably the clock can be seen as a stripped-down

Second version of the gk20a clock patches. I have tried to keep the therm and volt devices mandatory in the clock driver, but unfortunately they are too tied to bios to allow this, at least for the moment. Consequently this version is mostly a port of the first version to Ben's tree. Ben, please let me know what I have done wrong in terms of integration to your tree, as the main purpose of

This series does some refactoring in the GK20A's volt and clk drivers (fixing a few things while we are at it) to let GM20B benefit from the GK20A's logic with which it is compatible. GM20B is capable of more sophisticated (and power-efficient) reclocking which will follow later. Even after this more fancy reclocking is merged, the present logic will remain used in the lowest speedo of

This series adds support for GM20B PLL's Maxwell features, namely glitchless switch and (more importantly) DFS support. DFS lets the PLL lower its output speed according to input current variations, making the clock more stable and allowing it to run safely at lower voltage. All GM20B additions are done in the last patch, which consequently ends up being considerably big ; fortunately, it

...fine GPCPLL_CFG (SYS_GPCPLL_CFG_BASE + 0) >> +#define GPCPLL_CFG_ENABLE BIT(0) >> +#define GPCPLL_CFG_IDDQ BIT(1) >> +#define GPCPLL_CFG_LOCK_DET_OFF BIT(4) >> +#define GPCPLL_CFG_LOCK BIT(17) >> + >> +#define GPCPLL_COEFF (SYS_GPCPLL_CFG_BASE + 4) >> +#define GPCPLL_COEFF_M_SHIFT 0 >> +#define GPCPLL_COEFF_M_WIDTH 8 >> +#define GPCPLL_COEFF_N_SHIFT 8 >> +#define GPCPLL_COEFF_N_WIDTH 8 >> +#define GPCPLL_COEFF_P_SHIFT 16 >> +#define GPCPLL_COEFF_P_WIDTH 6 >...