search for: gpc2clk_out_bypdiv_width

...6 >> +#define GPC2CLK_OUT_VCODIV_SHIFT 8 >> +#define GPC2CLK_OUT_VCODIV1 0 >> +#define GPC2CLK_OUT_VCODIV_MASK >> (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \ >> + GPC2CLK_OUT_VCODIV_SHIFT) >> +#define GPC2CLK_OUT_BYPDIV_WIDTH 6 >> +#define GPC2CLK_OUT_BYPDIV_SHIFT 0 >> +#define GPC2CLK_OUT_BYPDIV31 0x3c >> +#define GPC2CLK_OUT_INIT_MASK ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << >> \ >> + GPC2CLK_OUT_SDIV14_INDIV4_SHIFT)\ >> +...

...> +#define GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 > +#define GPC2CLK_OUT_VCODIV_WIDTH 6 > +#define GPC2CLK_OUT_VCODIV_SHIFT 8 > +#define GPC2CLK_OUT_VCODIV1 0 > +#define GPC2CLK_OUT_VCODIV_MASK (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \ > + GPC2CLK_OUT_VCODIV_SHIFT) > +#define GPC2CLK_OUT_BYPDIV_WIDTH 6 > +#define GPC2CLK_OUT_BYPDIV_SHIFT 0 > +#define GPC2CLK_OUT_BYPDIV31 0x3c > +#define GPC2CLK_OUT_INIT_MASK ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \ > + GPC2CLK_OUT_SDIV14_INDIV4_SHIFT)\ > + | (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\ > +...

...GPC2CLK_OUT_SDIV14_INDIV4_SHIFT 31 +#define GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 +#define GPC2CLK_OUT_VCODIV_WIDTH 6 +#define GPC2CLK_OUT_VCODIV_SHIFT 8 +#define GPC2CLK_OUT_VCODIV1 0 +#define GPC2CLK_OUT_VCODIV_MASK (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \ + GPC2CLK_OUT_VCODIV_SHIFT) +#define GPC2CLK_OUT_BYPDIV_WIDTH 6 +#define GPC2CLK_OUT_BYPDIV_SHIFT 0 +#define GPC2CLK_OUT_BYPDIV31 0x3c +#define GPC2CLK_OUT_INIT_MASK ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \ + GPC2CLK_OUT_SDIV14_INDIV4_SHIFT)\ + | (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\ + | (MASK(GPC2CLK_OUT_BYPDIV_WID...

This series adds support for GM20B PLL's Maxwell features, namely glitchless switch and (more importantly) DFS support. DFS lets the PLL lower its output speed according to input current variations, making the clock more stable and allowing it to run safely at lower voltage. All GM20B additions are done in the last patch, which consequently ends up being considerably big ; fortunately, it

This series adds support for reclocking on GK20A. The first two patches touch the clock subsystem to allow GK20A to operate, by making the presence of the thermal and voltage devices optional, and allowing pstates to be provided directly instead of being probed using the BIOS (which Tegra does not have). The last patch adds the GK20A clock device. Arguably the clock can be seen as a stripped-down

Second version of the gk20a clock patches. I have tried to keep the therm and volt devices mandatory in the clock driver, but unfortunately they are too tied to bios to allow this, at least for the moment. Consequently this version is mostly a port of the first version to Ben's tree. Ben, please let me know what I have done wrong in terms of integration to your tree, as the main purpose of

This series does some refactoring in the GK20A's volt and clk drivers (fixing a few things while we are at it) to let GM20B benefit from the GK20A's logic with which it is compatible. GM20B is capable of more sophisticated (and power-efficient) reclocking which will follow later. Even after this more fancy reclocking is merged, the present logic will remain used in the lowest speedo of