search for: gp10b

...to have the related MODULE_FIRMWARE tag only on relevant arch (arm64). This will saves about 400k on initramfs when not relevant Signed-off-by: Nicolas Chauvet <kwizart at gmail.com> --- drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c | 2 ++ drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp10b.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c index 30491d132d59..df8b919dcf09 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/sub...

...vant arch (arm64). >> This will saves about 400k on initramfs when not relevant >> >> Signed-off-by: Nicolas Chauvet <kwizart at gmail.com> >> --- >> drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c | 2 ++ >> drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp10b.c | 2 ++ >> 2 files changed, 4 insertions(+) >> >> diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c >> index 30491d132d59..df8b919dcf09 100644 >> --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm...

...E tag only > on relevant arch (arm64). > This will saves about 400k on initramfs when not relevant > > Signed-off-by: Nicolas Chauvet <kwizart at gmail.com> > --- > drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c | 2 ++ > drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp10b.c | 2 ++ > 2 files changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c > index 30491d132d59..df8b919dcf09 100644 > --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c > +++ b/dr...

...eding at gmail.com> wrote: > > From: Thierry Reding <treding at nvidia.com> > > Hi Ben, > > here's a revised subset of the patches I had sent out a couple of weeks > ago. I've reworked the BAR2 accesses in the way that you had suggested, > which at least for GP10B turned out to be fairly trivial to do. I have > not looked in detail at this for GV11B yet, but a cursory look showed > that BAR2 is accessed in more places, so the equivalent for GV11B might > be a bit more involved. > > Other than that, not a lot has changed since then. I've ad...

GP10B's FB is largely compatible with the GP100 implementation, and only requires a few additional register inits. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/include/nvkm/subdev/fb.h | 1 + drm/nouveau/nvkm/subdev/fb/Kbuild | 1 + drm/nouveau/nvkm/subdev/fb...

From: Thierry Reding <treding at nvidia.com> gp10b doesn't have all the registers that gp102_gr_zbc wants to access, which causes IBUS MMIO faults to occur. Avoid this by using the gp100 variants of grctx and gr_zbc. Signed-off-by: Thierry Reding <treding at nvidia.com> --- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h | 1 + drivers/g...

From: Thierry Reding <treding at nvidia.com> Hi Ben, here's a revised subset of the patches I had sent out a couple of weeks ago. I've reworked the BAR2 accesses in the way that you had suggested, which at least for GP10B turned out to be fairly trivial to do. I have not looked in detail at this for GV11B yet, but a cursory look showed that BAR2 is accessed in more places, so the equivalent for GV11B might be a bit more involved. Other than that, not a lot has changed since then. I've added a couple of precurso...

GP10B is the chip used in Tegra X2 SoCs. This patchset adds support for its base engines after reworking secboot a bit to accomodate its calling convention better. This patchset has been tested rendering simple off-screen buffers using Mesa and yielded the expected result. Alexandre Courbot (15): sec...

...igned-off-by: Thierry Reding <treding at nvidia.com> --- Note that this is against Ben's tree, which should only hit linux-next tomorrow, so most people should not be hitting this yet. drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c | 9 +++++++-- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c | 9 +++++++-- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c index 6d5a13e4a857..82571032a07d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c +++ b/drivers/gpu/drm/nouv...

Hello everyone, it seems that GP10B support has regressed recently. With linux-next, I need to modify device/base.c to set .mmu = gp10b_mmu_new for GP10B (makes sense - I guess this was left as gf100_mmu_new as a typo) to probe. After that, running a trivial testcase (running a NOP method in 3D class) fails with [ 110.084649]...

GP10B's MC is compatible with GP100's, but engines need to be explicitly put out of ELPG during init. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/include/nvkm/subdev/mc.h | 1 + drm/nouveau/nvkm/subdev/mc/Kbuild | 1 + drm/nouveau/nvkm/subdev/mc/gp100.c...

On Mon, Sep 16, 2019 at 04:35:30PM +0100, Ben Dooks wrote: > On 16/09/2019 16:04, Thierry Reding wrote: > > From: Thierry Reding <treding at nvidia.com> > > > > There are extra registers that need to be programmed to make the level 2 > > cache work on GP10B, such as the stream ID register that is used when an > > SMMU is used to translate memory addresses. > > > > Signed-off-by: Thierry Reding <treding at nvidia.com> > > --- > > .../gpu/drm/nouveau/include/nvkm/subdev/ltc.h | 1 + > > .../gpu/drm/nouveau/...

...ot <acourbot at nvidia.com> --- drm/nouveau/include/nvkm/engine/gr.h | 1 + drm/nouveau/nvkm/engine/gr/Kbuild | 1 + drm/nouveau/nvkm/engine/gr/gf100.h | 4 +++ drm/nouveau/nvkm/engine/gr/gp100.c | 13 ++++++-- drm/nouveau/nvkm/engine/gr/gp102.c | 1 + drm/nouveau/nvkm/engine/gr/gp10b.c | 59 ++++++++++++++++++++++++++++++++++++ 6 files changed, 77 insertions(+), 2 deletions(-) create mode 100644 drm/nouveau/nvkm/engine/gr/gp10b.c diff --git a/drm/nouveau/include/nvkm/engine/gr.h b/drm/nouveau/include/nvkm/engine/gr.h index 0a636833e0eb..4e32e78de898 100644 --- a/drm/nouveau...

Bisection status report: The latest commit I have gotten to work is 10842ba074e9 drm/nouveau: remove unused nouveau_fence_work() i.e. the first bad commit is d7722134b825 drm/nouveau: switch over to new memory and vmm interfaces Even with the first one some patches/hacks are needed: - in mmu/gp10b.c, in the constructor we need to select the GM200 path - the GP100 path seems to not to work - as mentioned in the first mail, we need to set .mmu = gp10b_mmu_new, - and in nouveau_mem_memory_target we need to return NVKM_MEM_TARGET_NCOH instead of NVKM_MEM_TARGET_HOST. Cheers, Mikko On 11/10...

From: Thierry Reding <treding at nvidia.com> Hi Ben, here's a revised subset of the patches I had sent out a couple of weeks ago. I've reworked the BAR2 accesses in the way that you had suggested, which at least for GP10B turned out to be fairly trivial to do. I have not looked in detail at this for GV11B yet, but a cursory look showed that BAR2 is accessed in more places, so the equivalent for GV11B might be a bit more involved. Other than that, not a lot has changed since then. I've added a couple of precurso...

...16, 2019 at 04:35:30PM +0100, Ben Dooks wrote: > > On 16/09/2019 16:04, Thierry Reding wrote: > > > From: Thierry Reding <treding at nvidia.com> > > > > > > There are extra registers that need to be programmed to make the level 2 > > > cache work on GP10B, such as the stream ID register that is used when an > > > SMMU is used to translate memory addresses. > > > > > > Signed-off-by: Thierry Reding <treding at nvidia.com> > > > --- > > > .../gpu/drm/nouveau/include/nvkm/subdev/ltc.h | 1 + > &g...

GP10B uses the same 3D class as GP100. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c i...

From: Thierry Reding <treding at nvidia.com> Hi, the GPU on Jetson TX2 (GP10B) does not work properly on all devices. Why exactly is not clear, but there are slight differences between the SKUs that were tested. It turns out that the biggest issue is that on some devices (e.g. the one that I have), pulsing the GPU reset twice as is done in the current code (once as part of t...

...eau/nouveau_platform.c index 49d9ba0e3c51..1ada186fab77 100644 --- a/drm/nouveau/nouveau_platform.c +++ b/drm/nouveau/nouveau_platform.c @@ -62,6 +62,12 @@ static const struct nvkm_device_tegra_func gm20b_platform_data = { .require_ref_clk = true, }; +static const struct nvkm_device_tegra_func gp10b_platform_data = { + .iommu_bit = 36, + /* power provided by generic PM domains */ + .require_vdd = false, +}; + static const struct of_device_id nouveau_platform_match[] = { { .compatible = "nvidia,gk20a", @@ -71,6 +77,10 @@ static const struct of_device_id nouveau_platform_match[]...

...8PM +0100, Thierry Reding wrote: > From: Thierry Reding <treding at nvidia.com> > > Hi Ben, > > here's a revised subset of the patches I had sent out a couple of weeks > ago. I've reworked the BAR2 accesses in the way that you had suggested, > which at least for GP10B turned out to be fairly trivial to do. I have > not looked in detail at this for GV11B yet, but a cursory look showed > that BAR2 is accessed in more places, so the equivalent for GV11B might > be a bit more involved. > > Other than that, not a lot has changed since then. I've a...