search for: gp100_ltc_new

Displaying 16 results from an estimated 16 matches for "gp100_ltc_new".

Did you mean: gf100_ltc_new
2017 Aug 31
4
[RFC PATCH] drm/nouveau/therm: initial implementation of new gp1xx temperature sensor
...vers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index 7bdc7a5ae723..a6221b0996bf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -2166,6 +2166,7 @@ nv130_chipset = { .ltc = gp100_ltc_new, .mc = gp100_mc_new, .mmu = gf100_mmu_new, + .therm = gp100_therm_new, .secboot = gm200_secboot_new, .pci = gp100_pci_new, .pmu = gp100_pmu_new, @@ -2200,6 +2201,7 @@ nv132_chipset = { .ltc = gp100_ltc_new, .mc = gp100_mc_new, .mmu = gf100_mmu_new, + .therm = gp100_therm_new, .sec...
2017 Sep 01
0
[PATCH v2] drm/nouveau/therm: initial implementation of new gp1xx temperature sensor
...vers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index e096a5d9c292..28fd4fa98635 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -2169,6 +2169,7 @@ nv130_chipset = { .ltc = gp100_ltc_new, .mc = gp100_mc_new, .mmu = gf100_mmu_new, + .therm = gp100_therm_new, .secboot = gm200_secboot_new, .pci = gp100_pci_new, .pmu = gp100_pmu_new, @@ -2203,6 +2204,7 @@ nv132_chipset = { .ltc = gp100_ltc_new, .mc = gp100_mc_new, .mmu = gf100_mmu_new, + .therm = gp100_therm_new, .sec...
2016 Dec 12
2
[PATCH] drm/nouveau: fix unknown chipset for GTX 1060
...= { + .name = "GP104", + .bar = gf100_bar_new, + .bios = nvkm_bios_new, + .bus = gf100_bus_new, + .devinit = gm200_devinit_new, + .fb = gp104_fb_new, + .fuse = gm107_fuse_new, + .gpio = gk104_gpio_new, + .i2c = gm200_i2c_new, + .ibus = gm200_ibus_new, + .imem = nv50_instmem_new, + .ltc = gp100_ltc_new, + .mc = gp100_mc_new, + .mmu = gf100_mmu_new, + .pci = gp100_pci_new, + .timer = gk20a_timer_new, + .top = gk104_top_new, + .ce[0] = gp104_ce_new, + .ce[1] = gp104_ce_new, + .ce[2] = gp104_ce_new, + .ce[3] = gp104_ce_new, + .disp = gp104_disp_new, + .dma = gf119_dma_new, + .fifo = gp100_fifo_new,...
2017 Jan 22
1
[GP107 chipset][PATCH] Recognise GP107 chipset (GTX 1050/1050ti)
...os = nvkm_bios_new, > .bus = gf100_bus_new, > .devinit = gm200_devinit_new, > .fb = gp102_fb_new, > .fuse = gm107_fuse_new, > .gpio = gk104_gpio_new, > .i2c = gm200_i2c_new, > .ibus = gm200_ibus_new, > .imem = nv50_instmem_new, > .ltc = gp100_ltc_new, > .mc = gp100_mc_new, > .mmu = gf100_mmu_new, > .pci = gp100_pci_new, > .pmu = gp102_pmu_new, > .timer = gk20a_timer_new, > .top = gk104_top_new, > .ce[0] = gp102_ce_new, > .ce[1] = gp102_ce_new, > .ce[2] = gp102_ce_new, > .ce[3...
2017 Feb 14
1
[PATCH] drm/nouveau/core: recognise GP107 chipset
...= { + .name = "GP107", + .bar = gf100_bar_new, + .bios = nvkm_bios_new, + .bus = gf100_bus_new, + .devinit = gm200_devinit_new, + .fb = gp104_fb_new, + .fuse = gm107_fuse_new, + .gpio = gk104_gpio_new, + .i2c = gm200_i2c_new, + .ibus = gm200_ibus_new, + .imem = nv50_instmem_new, + .ltc = gp100_ltc_new, + .mc = gp100_mc_new, + .mmu = gf100_mmu_new, + .pci = gp100_pci_new, + .timer = gk20a_timer_new, + .top = gk104_top_new, + .ce[0] = gp104_ce_new, + .ce[1] = gp104_ce_new, + .ce[2] = gp104_ce_new, + .ce[3] = gp104_ce_new, + .disp = gp104_disp_new, + .dma = gf119_dma_new, + .fifo = gp100_fifo_new,...
2016 Dec 12
0
[PATCH] drm/nouveau: fix unknown chipset for GTX 1060
...ar_new, > + .bios = nvkm_bios_new, > + .bus = gf100_bus_new, > + .devinit = gm200_devinit_new, > + .fb = gp104_fb_new, > + .fuse = gm107_fuse_new, > + .gpio = gk104_gpio_new, > + .i2c = gm200_i2c_new, > + .ibus = gm200_ibus_new, > + .imem = nv50_instmem_new, > + .ltc = gp100_ltc_new, > + .mc = gp100_mc_new, > + .mmu = gf100_mmu_new, > + .pci = gp100_pci_new, > + .timer = gk20a_timer_new, > + .top = gk104_top_new, > + .ce[0] = gp104_ce_new, > + .ce[1] = gp104_ce_new, > + .ce[2] = gp104_ce_new, > + .ce[3] = gp104_ce_new, > + .disp = gp104_disp_new,...
2017 Feb 14
0
[PATCH] drm/nouveau/core: recognise GP107 chipset
...s = gf100_bus_new, > + .devinit = gm200_devinit_new, > + .fb = gp104_fb_new, > + .fuse = gm107_fuse_new, > + .gpio = gk104_gpio_new, > + .i2c = gm200_i2c_new, > + .ibus = gm200_ibus_new, > + .imem = nv50_instmem_new, > + .ltc = gp100_ltc_new, > + .mc = gp100_mc_new, > + .mmu = gf100_mmu_new, > + .pci = gp100_pci_new, > + .timer = gk20a_timer_new, > + .top = gk104_top_new, > + .ce[0] = gp104_ce_new, > + .ce[1] = gp104_ce_new, > + .ce[2] = gp104_ce_new, > +...
2017 Jul 03
0
[PATCH] initial support (display-only) for GP108
...= { + .name = "GP108", + .bar = gf100_bar_new, + .bios = nvkm_bios_new, + .bus = gf100_bus_new, + .devinit = gm200_devinit_new, + .fb = gp102_fb_new, + .fuse = gm107_fuse_new, + .gpio = gk104_gpio_new, + .i2c = gm200_i2c_new, + .ibus = gm200_ibus_new, + .imem = nv50_instmem_new, + .ltc = gp100_ltc_new, + .mc = gp100_mc_new, + .mmu = gf100_mmu_new, + .pci = gp100_pci_new, + .pmu = gp102_pmu_new, + .timer = gk20a_timer_new, + .top = gk104_top_new, + .ce[0] = gp102_ce_new, + .ce[1] = gp102_ce_new, + .ce[2] = gp102_ce_new, + .ce[3] = gp102_ce_new, + .disp = gp102_disp_new, + .dma = gf119_dma_new, +...
2017 Nov 10
2
GP10B regression
Hello everyone, it seems that GP10B support has regressed recently. With linux-next, I need to modify device/base.c to set .mmu = gp10b_mmu_new for GP10B (makes sense - I guess this was left as gf100_mmu_new as a typo) to probe. After that, running a trivial testcase (running a NOP method in 3D class) fails with [ 110.084649] nouveau 17000000.gpu: fifo: read fault at 0000011000 engine 06
2019 Sep 16
0
[PATCH 04/11] drm/nouveau: gp10b: Add custom L2 cache implementation
...ers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h > > +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h > > @@ -40,4 +40,5 @@ int gm107_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); > > int gm200_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); > > int gp100_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); > > int gp102_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); > > +int gp10b_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); > > #endif > > diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/dr...
2019 Sep 16
1
[PATCH 04/11] drm/nouveau: gp10b: Add custom L2 cache implementation
...include/nvkm/subdev/ltc.h > > > +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h > > > @@ -40,4 +40,5 @@ int gm107_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); > > > int gm200_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); > > > int gp100_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); > > > int gp102_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); > > > +int gp10b_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); > > > #endif > > > diff --git a/drivers/gpu/drm/nouveau/nvkm/engin...
2017 Nov 21
2
GP10B regression
Thanks to Thierry for finding this - applying index e14643615698..00eeaaffeae5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -2369,7 +2369,7 @@ nv13b_chipset = { .imem = gk20a_instmem_new, .ltc = gp100_ltc_new, .mc = gp10b_mc_new, - .mmu = gf100_mmu_new, + .mmu = gp10b_mmu_new, .secboot = gp10b_secboot_new, .pmu = gm20b_pmu_new, .timer = gk20a_timer_new, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/m...
2019 Sep 16
15
[PATCH 00/11] drm/nouveau: Enable GP10B by default
From: Thierry Reding <treding at nvidia.com> Hi, the GPU on Jetson TX2 (GP10B) does not work properly on all devices. Why exactly is not clear, but there are slight differences between the SKUs that were tested. It turns out that the biggest issue is that on some devices (e.g. the one that I have), pulsing the GPU reset twice as is done in the current code (once as part of the power-ungate
2019 Nov 02
13
[PATCH v2 0/9] drm/nouveau: Various fixes for GP10B
From: Thierry Reding <treding at nvidia.com> Hi Ben, here's a revised subset of the patches I had sent out a couple of weeks ago. I've reworked the BAR2 accesses in the way that you had suggested, which at least for GP10B turned out to be fairly trivial to do. I have not looked in detail at this for GV11B yet, but a cursory look showed that BAR2 is accessed in more places, so the
2019 Dec 09
11
[PATCH v3 0/9] drm/nouveau: Various fixes for GP10B
From: Thierry Reding <treding at nvidia.com> Hi Ben, here's a revised subset of the patches I had sent out a couple of weeks ago. I've reworked the BAR2 accesses in the way that you had suggested, which at least for GP10B turned out to be fairly trivial to do. I have not looked in detail at this for GV11B yet, but a cursory look showed that BAR2 is accessed in more places, so the
2017 Mar 29
15
[PATCH 00/15] Support for GP10B chipset
GP10B is the chip used in Tegra X2 SoCs. This patchset adds support for its base engines after reworking secboot a bit to accomodate its calling convention better. This patchset has been tested rendering simple off-screen buffers using Mesa and yielded the expected result. Alexandre Courbot (15): secboot: allow to boot multiple falcons secboot: pass instance to LS firmware loaders secboot: