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...march IMO. > > No. We'd still want to enable the architectural features for > vector intrinsics and the like. > > > I took this to mean that the feature should be enabled by default > for -march=skylake-avx512. > > > > Agreed. Yes. Also, GNOMETOYS clarified to me (off list) that is what he meant. -Hal > > -eric > > > > >> Based on the current performance data we're seeing, we think >> we need to ultimately default skylake-avx512 to >> -mprefer-vector-width=256. > >...

...al features for vector >>>> intrinsics and the like. >>>> >>> >>> I took this to mean that the feature should be enabled by default for >>> -march=skylake-avx512. >>> >> >> >> Agreed. >> >> >> Yes. Also, GNOMETOYS clarified to me (off list) that is what he meant. >> >> -Hal >> >> >> >> -eric >> >> >>> >>> >>> >>>> >>>> >>>> Based on the current performance data we're seeing, we think we need to...

Seems like something infinite-recursion like to me: $ clang --version clang version 6.0.0 (trunk 317833) Target: powerpc64le-unknown-linux-gnu $ clang -c test.ll warning: overriding the module target triple with powerpc64le-unknown-linux-gnu [-Woverride-module] ... #255 0x0000000012b07a78 llvm::DwarfUnit::getOrCreateTypeDIE(llvm::MDNode const*) ... So I'd say it reproduces. On Wed, Nov 15,

...linux or whatever > anyway, and completely ignore the change. This will mainly affect those > who build their own software and optimize for their system, and lots there > have probably caught on to this already. I always thought that's what > -march was made for, really. > > GNOMETOYS > > On Sat, Nov 11, 2017 at 10:25 AM, Sanjay Patel via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> Yes - I was thinking of FeatureFastScalarFSQRT / FeatureFastVectorFSQRT >> which are used by isFsqrtCheap(). These were added to override the default >> x8...

Hi all, I'm interested in obtaining the cycles spend by the CPU from LLVM and i was wondering if this was possible to obtain this with the scheduling information from LLVM. (For the cortex-m0 in particular). I found the following function : getInstrLatency() in the TargetInstrInfo class. If i sum the latencies of the instructions in a basic block i suppose i will get the total cycle cost

..., I just filed a bug on that last night. Your solutions look like > they'll help me extensively as cutting the size if half will prevent my > 80GB make install issues. > https://bugs.llvm.org/show_bug.cgi?id=35512 > > I'll leave the bug open for tracking purposes. > > GNOMETOYS > > On Mon, Dec 4, 2017 at 9:11 AM, George Rimar via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > > Hi all ! > > > > We have an issue with LLD, it is "relocation R_X86_64_32 out of range" > > (PR31109) > > which occurs during resolvi...

Hi all ! We have an issue with LLD, it is "relocation R_X86_64_32 out of range" (PR31109) which occurs during resolving relocations in debug sections. It looks happens because .debug_info section can be too large sometimes and 32x relocation is not enough to represent the value. One of possible solutions looks to be to deduplicate information to reduce .debug_info size. The rest of

...d for the standard x86_64-pc-linux or whatever anyway, and completely ignore the change. This will mainly affect those who build their own software and optimize for their system, and lots there have probably caught on to this already. I always thought that's what -march was made for, really. GNOMETOYS On Sat, Nov 11, 2017 at 10:25 AM, Sanjay Patel via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Yes - I was thinking of FeatureFastScalarFSQRT / FeatureFastVectorFSQRT > which are used by isFsqrtCheap(). These were added to override the default > x86 sqrt estimate codegen with:...

On Tue, Jan 16, 2018 at 11:13 PM, Martin J. O'Riordan <MartinO at theheart.ie> wrote: > Hi Sean, > > > > I had to add ‘v16f16’ to our out-of-tree target, and this was to > primarily to allow me to express lowering for all the OpenCL types (well, > except for the ‘v3T’ types). > > > > The trend does seem to be towards larger bit-width SIMD registers, and

Seems llvm cannot pass metadata to MachineInstr, or setting operand description in class Instruction and pass to class MachineInstr. Is it a good idea to extend llvm kernel structure to having this feature? Jonathan > On Nov 27, 2017, at 9:01 PM, Jatin Bhateja <jatin.bhateja at gmail.com> wrote: > > SelectionDAGBuilder contained within SelectionDAGISel has a map (NodeMap) b/w

I’m ok with that, but the reason I’m pushing is because there is no clear plan of action. Even if the plan of action is “When X happens, we can enable C++14”, that’s fine too. I just want to know, concretely, what is X. We should either be able to say never or give a reasonable set of conditions that would enable a switch. All I’ve seen though is “it’s hard” which just means I’m going to ask

Thanks for providing the experimental data! It clearly shows the value of type sections in DWARF. Regarding why type sections are off by default, aside from the issue of consumers needing to understand them, there is a size penalty to type sections that becomes more evident in smaller projects (meaning, fewer compilation units). The size penalty can be balanced against the amount of

> But where is the flat set? Maybe I can debug and check what is going on. The MCInstrDesc are in a table in lib/Target/PowerPC/PPCGenInstrInfo.inc of your build directory. > Some additional information: > > MCInst opcode: 0x7cb > Decode Index: 0x1e I had assumed this would have dissembled to '// Inst #234 = BC' which does have the branch flag set, but I think that

Are you referring to the X86TargetLowering::isFsqrtCheap hook? ~Craig On Fri, Nov 10, 2017 at 7:39 AM, Sanjay Patel <spatel at rotateright.com> wrote: > We can tie a user preference / override to a CPU model. We do something > like that for square root estimates already (although it does use a > SubtargetFeature currently for x86; ideally, we'd key that off of something >