search for: gm200

...he NVIDIA-released firmwares necessary to enable rendering on desktop and mobile Maxwell 2 GPUs. Kernel support is ready to be merged once this pull request is officially accepted. Thanks! ---------------------------------------------------------------- Alexandre Courbot (2): nvidia: Add GM200, GM204 and GM206 signed firmware nvidia: Add GM20B signed firmware WHENCE | 61 ++++++++++++++++++++++++++++++++++++- nvidia/gm200/acr/bl.bin | Bin 0 -> 832 bytes nvidia/gm200/acr/ucode_load.bin | Bin 0 -> 10144 bytes nvidia/gm200/acr...

The state of the falcons was not properly updated after running the unload ACR, which caused it to be run again (and thus fail) when nvkm_secboot_fini() was called during resume. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- Ben, please feel free to squash this into the gm200 secboot implementation patch - this fixes a bug that should not have been here to begin with. drm/nouveau/nvkm/subdev/secboot/gm200.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drm/nouveau/nvkm/subdev/secboot/gm200.c b/drm/nouveau/nvkm/subdev/secboot/gm200.c index 137c821213bb..cc100...

...ok at the linux-firmware branch we pushed earlier [1] you may already have an idea of the general organization, but this email is to discuss more specific details. Official firmware is organized per-chip, with an additional level of hierarchy for the different managed subsystems. For example, gm200 currently has two sub-directories, acr and gr, which contain the firmware files for secure boot (ACR) and PGRAPH (GR). ACR is a particular case and comes in the form of self-contained units (code, data, signature) that can be run on a high-secure falcon (currently PMU). It consumes a blob that...

...the instance block used for secure boot, instead of guessing through the presence of a RAM device. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- Ben, feel free to squash this one into the original secboot patch since it is a really minor fix. drm/nouveau/nvkm/subdev/secboot/gm200.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drm/nouveau/nvkm/subdev/secboot/gm200.c b/drm/nouveau/nvkm/subdev/secboot/gm200.c index b7ceba59dfb2..137c821213bb 100644 --- a/drm/nouveau/nvkm/subdev/secboot/gm200.c +++ b/drm/nouveau/nvkm/subdev/secboot/gm200.c @@ -1148,7 +114...

...r [1] you may already have an idea of the general >> organization, but this email is to discuss more specific details. >> >> Official firmware is organized per-chip, with an additional level of >> hierarchy for the different managed subsystems. >> >> For example, gm200 currently has two sub-directories, acr and gr, which >> contain the firmware files for secure boot (ACR) and PGRAPH (GR). >> >> ACR is a particular case and comes in the form of self-contained units >> (code, data, signature) that can be run on a high-secure falcon (currentl...

...2 GPUs. Signed-off-by: Karol Herbst <karolherbst at gmail.com> --- drm/nouveau/include/nvkm/subdev/therm.h | 1 + drm/nouveau/nvkm/engine/device/base.c | 3 +++ drm/nouveau/nvkm/subdev/therm/Kbuild | 1 + drm/nouveau/nvkm/subdev/therm/g84.c | 2 +- drm/nouveau/nvkm/subdev/therm/gm200.c | 39 +++++++++++++++++++++++++++++++++ drm/nouveau/nvkm/subdev/therm/priv.h | 1 + 6 files changed, 46 insertions(+), 1 deletion(-) create mode 100644 drm/nouveau/nvkm/subdev/therm/gm200.c diff --git a/drm/nouveau/include/nvkm/subdev/therm.h b/drm/nouveau/include/nvkm/subdev/therm.h inde...

...firmware loading requires the creation of gpuobj, a feature that is not available at that time. For this reason I have adopted this lazy and actually more resilient strategy. Alexandre Courbot (4): secboot: fix kerneldoc for secure boot structures gr/gf100: handle secure boot errors secboot/gm200: make firmware loading re-callable secboot: lazy-load firmware and be more resilient drm/nouveau/nvkm/engine/gr/gf100.c | 10 ++++- drm/nouveau/nvkm/subdev/secboot/base.c | 9 +---- drm/nouveau/nvkm/subdev/secboot/gm200.c | 72 ++++++++++++++++++++++++--------- drm/nouveau/nvkm/subdev/se...

...l >>>> organization, but this email is to discuss more specific details. >>>> >>>> Official firmware is organized per-chip, with an additional level of >>>> hierarchy for the different managed subsystems. >>>> >>>> For example, gm200 currently has two sub-directories, acr and gr, which >>>> contain the firmware files for secure boot (ACR) and PGRAPH (GR). >>>> >>>> ACR is a particular case and comes in the form of self-contained units >>>> (code, data, signature) that can be run o...

...b: add gm20b device drm/nouveau/include/nvkm/subdev/fb.h | 1 + drm/nouveau/nvkm/engine/device/base.c | 2 +- drm/nouveau/nvkm/subdev/fb/Kbuild | 1 + drm/nouveau/nvkm/subdev/fb/gf100.h | 4 ++++ drm/nouveau/nvkm/subdev/fb/gk20a.c | 20 ++++++------------ drm/nouveau/nvkm/subdev/fb/gm200.c | 2 +- drm/nouveau/nvkm/subdev/fb/gm20b.c | 40 +++++++++++++++++++++++++++++++++++ 7 files changed, 55 insertions(+), 15 deletions(-) create mode 100644 drm/nouveau/nvkm/subdev/fb/gm20b.c -- 2.10.0

...s email is to discuss more specific details. >>>>>> >>>>>> Official firmware is organized per-chip, with an additional level of >>>>>> hierarchy for the different managed subsystems. >>>>>> >>>>>> For example, gm200 currently has two sub-directories, acr and gr, which >>>>>> contain the firmware files for secure boot (ACR) and PGRAPH (GR). >>>>>> >>>>>> ACR is a particular case and comes in the form of self-contained units >>>>>> (code, da...

...rs that can be used to read the > WPR configuration. Use these registers instead of reaching into the > memory controller's register space to read the same information. > > Signed-off-by: Thierry Reding <treding at nvidia.com> > --- > .../drm/nouveau/nvkm/subdev/secboot/gm200.h | 2 +- > .../drm/nouveau/nvkm/subdev/secboot/gm20b.c | 81 ++++++++++++------- > .../drm/nouveau/nvkm/subdev/secboot/gp10b.c | 4 +- > 3 files changed, 53 insertions(+), 34 deletions(-) > > diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h b/drivers/gpu/drm/...

...branch we pushed earlier [1] you may already have an idea of the general > organization, but this email is to discuss more specific details. > > Official firmware is organized per-chip, with an additional level of > hierarchy for the different managed subsystems. > > For example, gm200 currently has two sub-directories, acr and gr, which > contain the firmware files for secure boot (ACR) and PGRAPH (GR). > > ACR is a particular case and comes in the form of self-contained units > (code, data, signature) that can be run on a high-secure falcon (currently > PMU). It...

gm20b's FB has the same capabilities as gm200, minus the ability to allocate RAM. Create a device that reflects this instead of re-using the gk20a device which may be incorrect. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/include/nvkm/subdev/fb.h | 1 + drm/nouveau/nvkm/engine/device/base.c | 2 +- drm/...

Hi everyone, I know, it's about f**king time and I apologize for the time it took us to finally put this together. m(__)m I have pushed two git branches which enable GM200 and GM204 (GM206 to follow soon) owners to finally load NVIDIA-provided signed firmware and start GR: - https://github.com/Gnurou/linux-firmware/tree/secboot contains the signed firmware for GM200 and GM204 (they are mostly the same). For each chip, "gr" contains the signed firmware...

...ve an idea of the general >>> organization, but this email is to discuss more specific details. >>> >>> Official firmware is organized per-chip, with an additional level of >>> hierarchy for the different managed subsystems. >>> >>> For example, gm200 currently has two sub-directories, acr and gr, which >>> contain the firmware files for secure boot (ACR) and PGRAPH (GR). >>> >>> ACR is a particular case and comes in the form of self-contained units >>> (code, data, signature) that can be run on a high-secure...

...h-secure falcon. This work is based on Deepak Goyal's initial port of Secure Boot to Nouveau. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/include/nvkm/subdev/secboot.h | 2 + drm/nouveau/nvkm/engine/device/base.c | 2 + drm/nouveau/nvkm/engine/gr/gm200.c | 8 +- drm/nouveau/nvkm/subdev/secboot/Kbuild | 1 + drm/nouveau/nvkm/subdev/secboot/gm200.c | 1485 +++++++++++++++++++++++++++++ drm/nouveau/nvkm/subdev/secboot/priv.h | 178 ++++ 6 files changed, 1669 insertions(+), 7 deletions(-) create mode 100644 drm/nouveau/nvkm/sub...

...rganization, but this email is to discuss more specific details. >>>>> >>>>> Official firmware is organized per-chip, with an additional level of >>>>> hierarchy for the different managed subsystems. >>>>> >>>>> For example, gm200 currently has two sub-directories, acr and gr, which >>>>> contain the firmware files for secure boot (ACR) and PGRAPH (GR). >>>>> >>>>> ACR is a particular case and comes in the form of self-contained units >>>>> (code, data, signature) t...

...nd on Tegra SoCs have registers that can be used to read the WPR configuration. Use these registers instead of reaching into the memory controller's register space to read the same information. Signed-off-by: Thierry Reding <treding at nvidia.com> --- .../drm/nouveau/nvkm/subdev/secboot/gm200.h | 2 +- .../drm/nouveau/nvkm/subdev/secboot/gm20b.c | 81 ++++++++++++------- .../drm/nouveau/nvkm/subdev/secboot/gp10b.c | 4 +- 3 files changed, 53 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secb...

Make sure we are not disturbed by spurious interrupts, as we poll the halt bit anyway. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/nvkm/subdev/secboot/gm200.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drm/nouveau/nvkm/subdev/secboot/gm200.c b/drm/nouveau/nvkm/subdev/secboot/gm200.c index 4932757ab1a2..5801babdf959 100644 --- a/drm/nouveau/nvkm/subdev/secboot/gm200.c +++ b/drm/nouveau/nvkm/subdev/secboot/gm200.c @@ -26,6 +26,7 @@ #inclu...

From: Ben Skeggs <bskeggs at redhat.com> [ Upstream commit 7adc77aa0e11f25b0e762859219c70852cd8d56f ] Method init is typically ordered by class in the FW image as ThreeD, TwoD, Compute. Due to a bug in parsing the FW into our internal format, we've been accidentally sending Twod + Compute methods to the ThreeD class, as well as Compute methods to the TwoD class - oops. Signed-off-by: