Displaying 20 results from an estimated 22 matches for "gm107_3d_class".
2014 May 27
2
[PATCH 1/2] nvc0: add GK20A 3D class
...0x00009297
> #define NVE4_3D_CLASS 0x0000a097
> #define NVF0_3D_CLASS 0x0000a197
> +#define NVEA_3D_CLASS 0x0000a297
> #define GM107_3D_CLASS 0x0000b097
> #define NV50_2D_CLASS 0x0000502d
> #define NVC0_2D_CLASS 0x0000902d
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/n...
2016 Feb 15
2
[PATCH 23/23] nvc0: implement support for maxwell texture headers
...nvc0/nvc0_screen.c
> @@ -991,6 +991,14 @@ nvc0_screen_create(struct nouveau_device *dev)
> PUSH_DATAh(push, screen->txc->offset);
> PUSH_DATA (push, screen->txc->offset);
> PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
> + if (screen->eng3d->oclass >= GM107_3D_CLASS) {
> + screen->tic.maxwell = true;
> + if (screen->eng3d->oclass == GM107_3D_CLASS) {
> + screen->tic.maxwell =
> + debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
> + IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxw...
2016 Feb 15
0
[PATCH 23/23] nvc0: implement support for maxwell texture headers
.../gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -991,6 +991,14 @@ nvc0_screen_create(struct nouveau_device *dev)
PUSH_DATAh(push, screen->txc->offset);
PUSH_DATA (push, screen->txc->offset);
PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
+ if (screen->eng3d->oclass >= GM107_3D_CLASS) {
+ screen->tic.maxwell = true;
+ if (screen->eng3d->oclass == GM107_3D_CLASS) {
+ screen->tic.maxwell =
+ debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
+ IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
+ }
+ }...
2016 Feb 15
0
[PATCH 23/23] nvc0: implement support for maxwell texture headers
...gt;> @@ -991,6 +991,14 @@ nvc0_screen_create(struct nouveau_device *dev)
>> PUSH_DATAh(push, screen->txc->offset);
>> PUSH_DATA (push, screen->txc->offset);
>> PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
>> + if (screen->eng3d->oclass >= GM107_3D_CLASS) {
>> + screen->tic.maxwell = true;
>> + if (screen->eng3d->oclass == GM107_3D_CLASS) {
>> + screen->tic.maxwell =
>> + debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
>> + IMMED_NVC0(push, SUBC_3D(0x0f10),...
2014 May 27
8
[PATCH 0/2] nvc0: support for GK20A (Tegra K1)
The following 2 patches make it possible to run Mesa programs on GK20A
(Tegra K1).
GK20A is very similar to GK104, but uses a new (backward-compatible) 3D class
as well as the same ISA as GK110 (SM35). Taking these differences into account
is sufficient to successfully render simple off-screen buffers.
Alexandre Courbot (2):
nvc0: add GK20A 3D class
nvc0: use SM35 ISA with GK20A
2015 Dec 19
2
[PATCH] nvc0: add hardware ETC2 and ASTC support where possible
...return false;
+ /* Restrict ETC2 and ASTC formats here. These are only supported on GM107+
+ * and GK20A.
+ */
+ if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
+ desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
+ nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
+ nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
+ return false;
+
/* transfers & shared are always supported */
bindings &= ~(PIPE_BIND_TRANSFER_READ |
PIPE_BIND_TRANSFER_WRITE |
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_tex....
2014 May 27
0
[PATCH 1/2] nvc0: add GK20A 3D class
...+++ b/src/gallium/drivers/nouveau/nv_object.xml.h
@@ -190,6 +190,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define NVC8_3D_CLASS 0x00009297
#define NVE4_3D_CLASS 0x0000a097
#define NVF0_3D_CLASS 0x0000a197
+#define NVEA_3D_CLASS 0x0000a297
#define GM107_3D_CLASS 0x0000b097
#define NV50_2D_CLASS 0x0000502d
#define NVC0_2D_CLASS 0x0000902d
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index cccfe2bba23d..95e5ef81cd79 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++...
2014 May 27
0
[PATCH 1/2] nvc0: add GK20A 3D class
...0x00009297
>> #define NVE4_3D_CLASS 0x0000a097
>> #define NVF0_3D_CLASS 0x0000a197
>> +#define NVEA_3D_CLASS 0x0000a297
>> #define GM107_3D_CLASS 0x0000b097
>> #define NV50_2D_CLASS 0x0000502d
>> #define NVC0_2D_CLASS 0x0000902d
>> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gal...
2014 Jul 10
3
[PATCH 0/3] nvc0: ARB_(multi_)draw_indirect support
The main patches are from Christoph. Unfortunately they're a little beyond my
understanding of all the vertex-related details, but they generally seemed
fine. I'm just going to push these unless someone steps up to review them.
Christoph Bumiller (2):
nvc0: add support for indirect drawing
nvc0: fix translate path for PRIM_RESTART_WITH_DRAW_ARRAYS
Ilia Mirkin (1):
nouveau: check if
2015 Dec 14
6
[Bug 93373] New: sometimes hickup with persistent garbaby
https://bugs.freedesktop.org/show_bug.cgi?id=93373
Bug ID: 93373
Summary: sometimes hickup with persistent garbaby
Product: xorg
Version: unspecified
Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
Severity: minor
Priority: medium
Component: Driver/nouveau
Assignee:
2015 Dec 19
0
[PATCH] nvc0: add hardware ETC2 and ASTC support where possible
...; + /* Restrict ETC2 and ASTC formats here. These are only supported on GM107+
> + * and GK20A.
> + */
> + if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
> + desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
> + nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
> + nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
> + return false;
> +
> /* transfers & shared are always supported */
> bindings &= ~(PIPE_BIND_TRANSFER_READ |
> PIPE_BIND_TRANSFER_WRITE |
> diff --git a/src/gal...
2014 Nov 19
5
[PATCH v2 0/3] nouveau: support for custom VRAM domains
This series is to allow NVIDIA chips with shared memory to operate more
efficiently (and to operate at all once we disable VRAM from the kernel
driver) by allowing nouveau_screen to specify a domain to use for objects
originally allocated into VRAM. If the domain is not overridden, the default
NOUVEAU_BO_VRAM is used. A NV_VRAM_DOMAIN() macro is then introduced to be
used in place of
2014 Nov 19
0
[PATCH v2 2/3] nvc0: use NV_VRAM_DOMAIN() macro
...gt;uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
for (i = 0; i < 5; ++i) {
/* TIC and TSC entries for each unit (nve4+ only) */
@@ -898,7 +898,7 @@ nvc0_screen_create(struct nouveau_device *dev)
PUSH_DATA (push, 0);
if (screen->eng3d->oclass < GM107_3D_CLASS) {
- ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
+ ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
&screen->poly_cache);
if (ret)
goto fail;
@@ -909,7...
2014 Nov 19
1
[PATCH v2 2/3] nvc0: use NV_VRAM_DOMAIN() macro
...->base) | NOUVEAU_BO_WR);
>
> for (i = 0; i < 5; ++i) {
> /* TIC and TSC entries for each unit (nve4+ only) */
> @@ -898,7 +898,7 @@ nvc0_screen_create(struct nouveau_device *dev)
> PUSH_DATA (push, 0);
>
> if (screen->eng3d->oclass < GM107_3D_CLASS) {
> - ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
> + ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
> &screen->poly_cache);
> if (ret)
>...
2014 Nov 19
1
[PATCH v2 2/3] nvc0: use NV_VRAM_DOMAIN() macro
...amp;screen->base) | NOUVEAU_BO_WR);
>
> for (i = 0; i < 5; ++i) {
> /* TIC and TSC entries for each unit (nve4+ only) */
> @@ -898,7 +898,7 @@ nvc0_screen_create(struct nouveau_device *dev)
> PUSH_DATA (push, 0);
>
> if (screen->eng3d->oclass < GM107_3D_CLASS) {
> - ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
> + ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
> &screen->poly_cache);
> if (ret)
>...
2014 Oct 27
4
[PATCH 0/3] nouveau: support for custom VRAM domains
This series is to allow NVIDIA chips with shared memory to operate more
efficiently (and to operate at all once we disable VRAM from the kernel
driver) by allowing nouveau_screen to specify a domain to use for objects
originally allocated into VRAM. If the domain is not overridden, the default
NOUVEAU_BO_VRAM is used. A NV_VRAM_DOMAIN() macro is then introduced to be
used in place of
2015 Jun 19
5
[PATCH v3 0/2] nouveau: support for custom VRAM domains
New revision of this patchset that prevents VRAM objects from being
allocated on VRAM-less systems like Tegra. This is required for Mesa
to work on such systems.
Changes since v2:
- Use vram_size to detect systems without VRAM and set the correct
domain instead of expecting each chip to set its domain explicitly.
Alexandre Courbot (2):
nouveau: support for custom VRAM domains
nvc0: use
2016 Feb 15
24
[PATCH 01/23] nv50: import updated g80_defs.xml.h from rnndb
From: Ben Skeggs <bskeggs at redhat.com>
Signed-off-by: Ben Skeggs <bskeggs at redhat.com>
---
src/gallium/drivers/nouveau/nv50/g80_defs.xml.h | 279 ++++++++++++++++++++++++
1 file changed, 279 insertions(+)
create mode 100644 src/gallium/drivers/nouveau/nv50/g80_defs.xml.h
diff --git a/src/gallium/drivers/nouveau/nv50/g80_defs.xml.h
2014 Jun 17
0
[PATCH try 2 2/2] gallium/nouveau: move pushbuf and fences to context
...(push, NVC0_2D_COND_MODE_ALWAYS);
-
- BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
- PUSH_DATAh(push, screen->fence.bo->offset + 16);
- PUSH_DATA (push, screen->fence.bo->offset + 16);
-
switch (dev->chipset & ~0xf) {
case 0x110:
obj_class = GM107_3D_CLASS;
@@ -750,6 +672,95 @@ nvc0_screen_create(struct nouveau_device *dev)
FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
screen->base.class_3d = obj_class;
+ ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
+...
2014 Jun 17
2
[PATCH try 2 1/2] gallium/nouveau: decouple nouveau_fence implementation from screen
Signed-off-by: Maarten Lankhorst <maarten.lankhorst at canonical.com>
---
src/gallium/drivers/nouveau/nouveau_fence.c | 76 ++++++++++++-------------
src/gallium/drivers/nouveau/nouveau_fence.h | 22 +++++--
src/gallium/drivers/nouveau/nouveau_screen.c | 9 +++
src/gallium/drivers/nouveau/nouveau_screen.h | 14 ++---
src/gallium/drivers/nouveau/nv30/nv30_context.c | 4 +-