Displaying 1 result from an estimated 1 matches for "gluelessly".
2005 Jun 21
9
[OT] Memory Models and Multi/Virtual-Cores -- WAS: 4.0 -> 4.1 update failing
...step. This is little more
than slapping in a second set of all the non-SRAM transistors, plus
any additional bridging logic, if necessary. AMD HyperTransport
requires none -- as HyperTransport can "tunnel" anything, EV6
memory/addressing, I/O tunnels/bridges, inter-CPU, etc... all
"gluelessly." Intel MCH GTL+ cannot, and requires bridges between
the "chipset MCH" and the "multi-core MCH," adding latency. And
there are nagging 32-bit limitations with GTL+ as well (long story).
The next logical evolution in microprocessor design is to blur the
physical separati...