search for: gk20a_pstates

...LK_OUT_SHIFT), 0); + + _gk20a_pllg_disable(priv); +} + +#define GK20A_CLK_GPC_MDIV 1000 + +static struct nouveau_clocks +gk20a_domains[] = { + { nv_clk_src_crystal, 0xff }, + { nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV }, + { nv_clk_src_max } +}; + +static struct nouveau_pstate +gk20a_pstates[] = { + { + .base = { + .domain[nv_clk_src_gpc] = 72000, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 108000, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 180000, + }, + }, + { + .base = { + .domain[nv_clk_src_gpc] = 252000, + }, + }, + { + .base = { + .domain[n...

...> +#define GK20A_CLK_GPC_MDIV 1000 > + > +static struct nouveau_clocks > +gk20a_domains[] = { > + { nv_clk_src_crystal, 0xff }, > + { nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV }, > + { nv_clk_src_max } > +}; > + > +static struct nouveau_pstate > +gk20a_pstates[] = { > + { > + .base = { > + .domain[nv_clk_src_gpc] = 72000, > + }, > + }, > + { > + .base = { > + .domain[nv_clk_src_gpc] = 108000, > + }, > + }, > + { > + .base = { > + .domain[nv_clk_src_gpc] = 180000, > + }, > + }, > + { > + .bas...

This series adds support for reclocking on GK20A. The first two patches touch the clock subsystem to allow GK20A to operate, by making the presence of the thermal and voltage devices optional, and allowing pstates to be provided directly instead of being probed using the BIOS (which Tegra does not have). The last patch adds the GK20A clock device. Arguably the clock can be seen as a stripped-down

Second version of the gk20a clock patches. I have tried to keep the therm and volt devices mandatory in the clock driver, but unfortunately they are too tied to bios to allow this, at least for the moment. Consequently this version is mostly a port of the first version to Ben's tree. Ben, please let me know what I have done wrong in terms of integration to your tree, as the main purpose of

...nouveau/nvkm/subdev/clk/gk20a.c index 5f0ee24..8b64cc9 100644 --- a/drm/nouveau/nvkm/subdev/clk/gk20a.c +++ b/drm/nouveau/nvkm/subdev/clk/gk20a.c @@ -636,6 +636,7 @@ gk20a_clk = { .calc = gk20a_clk_calc, .prog = gk20a_clk_prog, .tidy = gk20a_clk_tidy, + .update = nv40_clk_update, .pstates = gk20a_pstates, .nr_pstates = ARRAY_SIZE(gk20a_pstates), .domains = { diff --git a/drm/nouveau/nvkm/subdev/clk/gm20b.c b/drm/nouveau/nvkm/subdev/clk/gm20b.c index 71b2bbb..8c8eb8c 100644 --- a/drm/nouveau/nvkm/subdev/clk/gm20b.c +++ b/drm/nouveau/nvkm/subdev/clk/gm20b.c @@ -168,6 +168,7 @@ gm20b_clk_speedo0 =...

...t(struct nouveau_volt *); > int nouveau_voltgpio_get(struct nouveau_volt *); > diff --git a/nvkm/subdev/clock/gk20a.c b/nvkm/subdev/clock/gk20a.c > index 82abbea2be12..fb4fad374bdd 100644 > --- a/nvkm/subdev/clock/gk20a.c > +++ b/nvkm/subdev/clock/gk20a.c > @@ -470,76 +470,91 @@ gk20a_pstates[] = { > { > .base = { > .domain[nv_clk_src_gpc] = 72000, > + .voltage = 0, > }, > }, > { > .base = { > .domain[nv_clk_src_gpc] = 108000, > + .voltage = 1, > }, > }, > { > .base = { > .domain[nv_clk_sr...

This series does some refactoring in the GK20A's volt and clk drivers (fixing a few things while we are at it) to let GM20B benefit from the GK20A's logic with which it is compatible. GM20B is capable of more sophisticated (and power-efficient) reclocking which will follow later. Even after this more fancy reclocking is merged, the present logic will remain used in the lowest speedo of

...veau_voltgpio_get(struct nouveau_volt *); >>> diff --git a/nvkm/subdev/clock/gk20a.c b/nvkm/subdev/clock/gk20a.c >>> index 82abbea2be12..fb4fad374bdd 100644 >>> --- a/nvkm/subdev/clock/gk20a.c >>> +++ b/nvkm/subdev/clock/gk20a.c >>> @@ -470,76 +470,91 @@ gk20a_pstates[] = { >>> { >>> .base = { >>> .domain[nv_clk_src_gpc] = 72000, >>> + .voltage = 0, >>> }, >>> }, >>> { >>> .base = { >>> .domain[nv...

...ruct nouveau_volt *); >>>> diff --git a/nvkm/subdev/clock/gk20a.c b/nvkm/subdev/clock/gk20a.c >>>> index 82abbea2be12..fb4fad374bdd 100644 >>>> --- a/nvkm/subdev/clock/gk20a.c >>>> +++ b/nvkm/subdev/clock/gk20a.c >>>> @@ -470,76 +470,91 @@ gk20a_pstates[] = { >>>> { >>>> .base = { >>>> .domain[nv_clk_src_gpc] = 72000, >>>> + .voltage = 0, >>>> }, >>>> }, >>>> { >>>> .base = { >&...

...ss; int nouveau_voltgpio_init(struct nouveau_volt *); int nouveau_voltgpio_get(struct nouveau_volt *); diff --git a/nvkm/subdev/clock/gk20a.c b/nvkm/subdev/clock/gk20a.c index 82abbea2be12..fb4fad374bdd 100644 --- a/nvkm/subdev/clock/gk20a.c +++ b/nvkm/subdev/clock/gk20a.c @@ -470,76 +470,91 @@ gk20a_pstates[] = { { .base = { .domain[nv_clk_src_gpc] = 72000, + .voltage = 0, }, }, { .base = { .domain[nv_clk_src_gpc] = 108000, + .voltage = 1, }, }, { .base = { .domain[nv_clk_src_gpc] = 180000, + .voltage = 2, }, }, { .base = { .domain[nv_clk_src_gp...

...ss; int nouveau_voltgpio_init(struct nouveau_volt *); int nouveau_voltgpio_get(struct nouveau_volt *); diff --git a/nvkm/subdev/clock/gk20a.c b/nvkm/subdev/clock/gk20a.c index 82abbea2be12..fb4fad374bdd 100644 --- a/nvkm/subdev/clock/gk20a.c +++ b/nvkm/subdev/clock/gk20a.c @@ -470,76 +470,91 @@ gk20a_pstates[] = { { .base = { .domain[nv_clk_src_gpc] = 72000, + .voltage = 0, }, }, { .base = { .domain[nv_clk_src_gpc] = 108000, + .voltage = 1, }, }, { .base = { .domain[nv_clk_src_gpc] = 180000, + .voltage = 2, }, }, { .base = { .domain[nv_clk_src_gp...

Some Tegra drivers might be complied as kernel modules, and they need the fuse information for initialization. One example is the GK20A Nouveau driver. It needs the GPU speedo value to calculate frequency-voltage table. So export the tegra_sku_info. Signed-off-by: Vince Hsu <vinceh at nvidia.com> --- v2: add more description why we need this patch drivers/soc/tegra/fuse/fuse-tegra.c | 1

...; >> int nouveau_voltgpio_get(struct nouveau_volt *); >> diff --git a/nvkm/subdev/clock/gk20a.c b/nvkm/subdev/clock/gk20a.c >> index 82abbea2be12..fb4fad374bdd 100644 >> --- a/nvkm/subdev/clock/gk20a.c >> +++ b/nvkm/subdev/clock/gk20a.c >> @@ -470,76 +470,91 @@ gk20a_pstates[] = { >> { >> .base = { >> .domain[nv_clk_src_gpc] = 72000, >> + .voltage = 0, >> }, >> }, >> { >> .base = { >> .domain[nv_clk_src_gpc] = 108000, >> +...

Signed-off-by: Vince Hsu <vinceh at nvidia.com> --- nvkm/subdev/volt/base.c | 67 ++++++++++++++++++++++++++++--------------------- 1 file changed, 38 insertions(+), 29 deletions(-) diff --git a/nvkm/subdev/volt/base.c b/nvkm/subdev/volt/base.c index 32794a999106..26ccd8df193f 100644 --- a/nvkm/subdev/volt/base.c +++ b/nvkm/subdev/volt/base.c @@ -101,6 +101,41 @@ nouveau_volt_set_id(struct

Some Tegra drivers might be compiled as kernel modules, and they need the fuse information for initialization. One example is the GK20A Nouveau driver. It needs the GPU speedo value to calculate frequency-voltage table. So export the tegra_sku_info. Signed-off-by: Vince Hsu <vinceh at nvidia.com> Acked-by: Alexandre Courbot <acourbot at nvidia.com> Acked-by: Thierry Reding <treding

Some Tegra drivers might be compiled as kernel modules, and they need the fuse information for initialization. One example is the GK20A Nouveau driver. It needs the GPU speedo value to calculate frequency-voltage table. So export the tegra_sku_info. Signed-off-by: Vince Hsu <vinceh at nvidia.com> Acked-by: Alexandre Courbot <acourbot at nvidia.com> Acked-by: Thierry Reding <treding

This series addresses various issues inside the reclocking code: 1. after resume the set clocks are reset 2. reclocking not possible while GPU is suspended 3. nouveau always does full reclocks even if only a change of the voltage is required Some of the patches were part of the bigger reclocking series I sent months ago, some things have changed though. This is also preparation work of

We are slowly getting there! v4 of the series with some realy good improvements, so I am sure this is like 95% done and only needs some proper polishing and proper Reviews! I also added the NvVoltOffsetmV module parameter, so that a user is able to over and !under!-volt the GPU. Overvolting makes sense, when there are still some reclocking issues left, which might be solved by a higher voltage.