search for: gk20a_pmu_dvfs_data

nvkm_mm_fini() was not called when exiting the driver, resulting in a memory leak. Fix this. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/nouveau_platform.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drm/nouveau/nouveau_platform.c b/drm/nouveau/nouveau_platform.c index 3691982452a9..f83aa12ee5c6 100644 --- a/drm/nouveau/nouveau_platform.c +++

...*pmu, int *state) > -{ > - struct nvkm_clk *clk = pmu->base.subdev.device->clk; > - > - *state = clk->pstate; > - return 0; > -} > - > -static int > gk20a_pmu_dvfs_get_target_state(struct gk20a_pmu *pmu, > int *state, int load) > { > struct gk20a_pmu_dvfs_data *data = pmu->data; > struct nvkm_clk *clk = pmu->base.subdev.device->clk; > + struct nvkm_pstate *pstate = clk->pstate; > int cur_level, level; > > + if (!pstate) { > + *state = 0; > + return 1; > + } > + > /* For GK20A, the performance level...

...sg_unhandled_cmd { + u8 msg_type; + u8 unit_id; +}; + +struct pmu_rc_msg { + u8 msg_type; + struct pmu_rc_msg_unhandled_cmd unhandled_cmd; +}; + +/*pmu generic msg format*/ +struct pmu_msg { + struct pmu_hdr hdr; + union { + struct pmu_init_msg init; + struct pmu_rc_msg rc; + } msg; +}; struct gk20a_pmu_dvfs_data { int p_load_target; @@ -39,8 +211,19 @@ struct gk20a_pmu_priv { struct nvkm_pmu base; struct nvkm_alarm alarm; struct gk20a_pmu_dvfs_data *data; + struct pmu_ucode_desc *desc; + struct pmu_buf_desc ucode; + struct pmu_buf_desc trace_buf; + struct mutex pmu_copy_lock; + bool pmu_ready; + in...

...tate(struct gk20a_pmu *pmu, int *state) > -{ > - struct nvkm_clk *clk = pmu->base.subdev.device->clk; > - > - *state = clk->pstate; > -} > - > static int > gk20a_pmu_dvfs_get_target_state(struct gk20a_pmu *pmu, > int *state, int load) > { > struct gk20a_pmu_dvfs_data *data = pmu->data; > struct nvkm_clk *clk = pmu->base.subdev.device->clk; > + struct nvkm_pstate *pstate = clk->pstate; > int cur_level, level; > > + if (!pstate) { > + *state = 0; > + return 1; > + } > + > /* For GK20A, the performance level is d...

...} static int -gk20a_pmu_dvfs_get_cur_state(struct gk20a_pmu *pmu, int *state) -{ - struct nvkm_clk *clk = pmu->base.subdev.device->clk; - - *state = clk->pstate; - return 0; -} - -static int gk20a_pmu_dvfs_get_target_state(struct gk20a_pmu *pmu, int *state, int load) { struct gk20a_pmu_dvfs_data *data = pmu->data; struct nvkm_clk *clk = pmu->base.subdev.device->clk; + struct nvkm_pstate *pstate = clk->pstate; int cur_level, level; + if (!pstate) { + *state = 0; + return 1; + } + /* For GK20A, the performance level is directly mapped to pstate */ - level = cur_level =...

...->clk; >> - >> - *state = clk->pstate; >> - return 0; >> -} >> - >> -static int >> gk20a_pmu_dvfs_get_target_state(struct gk20a_pmu *pmu, >> int *state, int load) >> { >> struct gk20a_pmu_dvfs_data *data = pmu->data; >> struct nvkm_clk *clk = pmu->base.subdev.device->clk; >> + struct nvkm_pstate *pstate = clk->pstate; >> int cur_level, level; >> + if (!pstate) { >> + *state = 0; >> + return...

...0, false); } -static void -gk20a_pmu_dvfs_get_cur_state(struct gk20a_pmu *pmu, int *state) -{ - struct nvkm_clk *clk = pmu->base.subdev.device->clk; - - *state = clk->pstate; -} - static int gk20a_pmu_dvfs_get_target_state(struct gk20a_pmu *pmu, int *state, int load) { struct gk20a_pmu_dvfs_data *data = pmu->data; struct nvkm_clk *clk = pmu->base.subdev.device->clk; + struct nvkm_pstate *pstate = clk->pstate; int cur_level, level; + if (!pstate) { + *state = 0; + return 1; + } + /* For GK20A, the performance level is directly mapped to pstate */ - level = cur_level =...

...0, false); } -static void -gk20a_pmu_dvfs_get_cur_state(struct gk20a_pmu *pmu, int *state) -{ - struct nvkm_clk *clk = pmu->base.subdev.device->clk; - - *state = clk->pstate; -} - static int gk20a_pmu_dvfs_get_target_state(struct gk20a_pmu *pmu, int *state, int load) { struct gk20a_pmu_dvfs_data *data = pmu->data; struct nvkm_clk *clk = pmu->base.subdev.device->clk; + struct nvkm_pstate *pstate = clk->pstate; int cur_level, level; + if (!pstate) { + *state = 0; + return 1; + } + /* For GK20A, the performance level is directly mapped to pstate */ - level = cur_level =...

...>> + >> +/*pmu generic msg format*/ >> +struct pmu_msg { >> + struct pmu_hdr hdr; >> + union { >> + struct pmu_init_msg init; >> + struct pmu_rc_msg rc; >> + } msg; >> +}; >> >> struct gk20a_pmu_dvfs_data { >> int p_load_target; >> @@ -39,8 +211,19 @@ struct gk20a_pmu_priv { >> struct nvkm_pmu base; >> struct nvkm_alarm alarm; >> struct gk20a_pmu_dvfs_data *data; >> + struct pmu_ucode_desc *desc; >> + struct pmu_bu...

...{ + u8 msg_type; + struct pmu_rc_msg_unhandled_cmd unhandled_cmd; +}; + +struct pmu_msg { + struct pmu_hdr hdr; + union { + struct pmu_init_msg init; + struct pmu_rc_msg rc; + } msg; +}; + #define BUSY_SLOT 0 #define CLK_SLOT 7 +#define GK20A_PMU_UCODE_IMAGE "gpmu_ucode.bin" struct gk20a_pmu_dvfs_data { int p_load_target; @@ -39,8 +206,22 @@ struct gk20a_pmu_priv { struct nvkm_pmu base; struct nvkm_alarm alarm; struct gk20a_pmu_dvfs_data *data; + struct pmu_ucode_desc *desc; + struct pmu_buf_desc ucode; + struct pmu_buf_desc trace_buf; + struct mutex pmu_copy_lock; + bool pmu_ready; + in...

This series addresses various issues inside the reclocking code: 1. after resume the set clocks are reset 2. reclocking not possible while GPU is suspended Some of the patches were part of the bigger reclocking series I sent months ago, some things have changed though. This is also preparation work of changing the clock state due to temperature changes and dynamic reclocking. v2: remove commits

This series addresses various issues inside the reclocking code: 1. after resume the set clocks are reset 2. reclocking not possible while GPU is suspended 3. racy reclocking while GPU is suspending and leading to hangs Some of the patches were part of the bigger reclocking series I sent months ago, some things have changed though. This is also preparation work of changing the clock state due to

This series addresses various issues inside the reclocking code: 1. after resume the set clocks are reset 2. reclocking not possible while GPU is suspended 3. nouveau always does full reclocks even if only a change of the voltage is required Some of the patches were part of the bigger reclocking series I sent months ago, some things have changed though. This is also preparation work of

Adds Nouveau controlled thermal throttling for Kepler+ GPUs. With this I feel safe enough to add support for Maxwell2 reclocking later on (still hidden behind a switch, but we can be fairly sure to not overheat hardware if a user isn't carefull enough) Contains all patches from my clk update series, but I thought it makes sense to include those in this series as well for completness. Please

...t; +static int gk20a_init_pmu_setup_sw(struct nvkm_pmu *ppmu); > +static int gk20a_init_pmu_setup_hw1(struct nvkm_pmu *ppmu, struct nvkm_mc *pmc); > +static void gk20a_pmu_intr(struct nvkm_subdev *subdev); > > +static void gk20a_pmu_pgob(struct nvkm_pmu *ppmu, bool enable); > struct gk20a_pmu_dvfs_data { > int p_load_target; > int p_load_max; > int p_smooth; > unsigned int avg_load; > }; > - > struct gk20a_pmu_priv { > struct nvkm_pmu base; > struct nvkm_alarm alarm; > @@ -46,7 +92,30 @@ struct gk20a_pmu_dvfs_dev_stat...

Just wanted to post updated versions of my last series/patches. Reviews welcomed. It would be also nice if we agree on features I should focus upstreaming, so that this work can be better splitted or reordered. Sadly most of my patches depend on the rather big clk subdev rework and I think those patches shows best, why I think this rework is actually needed and makes things much easier to add

...t struct firmware **pfw); +static int gk20a_init_pmu_setup_sw(struct nvkm_pmu *ppmu); +static int gk20a_init_pmu_setup_hw1(struct nvkm_pmu *ppmu, struct nvkm_mc *pmc); +static void gk20a_pmu_intr(struct nvkm_subdev *subdev); +static void gk20a_pmu_pgob(struct nvkm_pmu *ppmu, bool enable); struct gk20a_pmu_dvfs_data { int p_load_target; int p_load_max; int p_smooth; unsigned int avg_load; }; - struct gk20a_pmu_priv { struct nvkm_pmu base; struct nvkm_alarm alarm; @@ -46,7 +92,30 @@ struct gk20a_pmu_dvfs_dev_status { unsigned long busy; int cur_state; }; - +int gk20a_pmu_debugfs_init(struct n...

...t; +static int gk20a_init_pmu_setup_sw(struct nvkm_pmu *ppmu); > +static int gk20a_init_pmu_setup_hw1(struct nvkm_pmu *ppmu, struct nvkm_mc *pmc); > +static void gk20a_pmu_intr(struct nvkm_subdev *subdev); > > +static void gk20a_pmu_pgob(struct nvkm_pmu *ppmu, bool enable); > struct gk20a_pmu_dvfs_data { > int p_load_target; > int p_load_max; > int p_smooth; > unsigned int avg_load; > }; > - > struct gk20a_pmu_priv { > struct nvkm_pmu base; > struct nvkm_alarm alarm; > @@ -46,7 +92,30 @@ struct gk20a_pmu_dvfs_dev_stat...

This is an updated series for the old clocking improvement one. I think I got everything needed in place and also a simple update mechanism for updating the cstates/voltage on temperature changes. If anything is unclear how I REed or got the information, please leave a note so that I can provide additional information in the commits. Besides that I think we are pretty close now and only some

We are slowly getting there! v4 of the series with some realy good improvements, so I am sure this is like 95% done and only needs some proper polishing and proper Reviews! I also added the NvVoltOffsetmV module parameter, so that a user is able to over and !under!-volt the GPU. Overvolting makes sense, when there are still some reclocking issues left, which might be solved by a higher voltage.