search for: gk20a_instmem_new

.../gk20a.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drm/nouveau/nvkm/subdev/instmem/gk20a.c b/drm/nouveau/nvkm/subdev/instmem/gk20a.c index 6b8f2a19b2d9..4c3c744c5c6b 100644 --- a/drm/nouveau/nvkm/subdev/instmem/gk20a.c +++ b/drm/nouveau/nvkm/subdev/instmem/gk20a.c @@ -576,6 +576,7 @@ gk20a_instmem_new(struct nvkm_device *device, int index, { struct nvkm_device_tegra *tdev = device->func->tegra(device); struct gk20a_instmem *imem; + int ret; if (!(imem = kzalloc(sizeof(*imem), GFP_KERNEL))) return -ENOMEM; @@ -583,6 +584,10 @@ gk20a_instmem_new(struct nvkm_device *device, int in...

...dy been recycled */ if (node->base.vaddr) gk20a_instobj_iommu_recycle_vaddr(node); - spin_unlock_irqrestore(&imem->lock, flags); + mutex_unlock(&imem->lock); r = list_first_entry(&node->base.mem.regions, struct nvkm_mm_node, rl_entry); @@ -580,7 +577,7 @@ gk20a_instmem_new(struct nvkm_device *device, int index, if (!(imem = kzalloc(sizeof(*imem), GFP_KERNEL))) return -ENOMEM; nvkm_instmem_ctor(&gk20a_instmem, device, index, &imem->base); - spin_lock_init(&imem->lock); + mutex_init(&imem->lock); *pimem = &imem->base; /* do...

...tobj_iommu_recycle_vaddr(node); >> >> - spin_unlock_irqrestore(&imem->lock, flags); >> + mutex_unlock(&imem->lock); >> >> r = list_first_entry(&node->base.mem.regions, struct nvkm_mm_node, >> rl_entry); >> @@ -580,7 +577,7 @@ gk20a_instmem_new(struct nvkm_device *device, int index, >> if (!(imem = kzalloc(sizeof(*imem), GFP_KERNEL))) >> return -ENOMEM; >> nvkm_instmem_ctor(&gk20a_instmem, device, index, &imem->base); >> - spin_lock_init(&imem->lock); >> + mutex_init(&imem->loc...

...gt;base.vaddr = dma_alloc_attrs(dev, npages << PAGE_SHIFT, &node->handle, GFP_KERNEL, - &imem->attrs); + imem->attrs); if (!node->base.vaddr) { nvkm_error(subdev, "cannot allocate DMA memory\n"); return -ENOMEM; @@ -597,10 +597,9 @@ gk20a_instmem_new(struct nvkm_device *device, int index, nvkm_info(&imem->base.subdev, "using IOMMU\n"); } else { - init_dma_attrs(&imem->attrs); - dma_set_attr(DMA_ATTR_NON_CONSISTENT, &imem->attrs); - dma_set_attr(DMA_ATTR_WEAK_ORDERING, &imem->attrs); - dma_set_att...

...gt;base.vaddr = dma_alloc_attrs(dev, npages << PAGE_SHIFT, &node->handle, GFP_KERNEL, - &imem->attrs); + imem->attrs); if (!node->base.vaddr) { nvkm_error(subdev, "cannot allocate DMA memory\n"); return -ENOMEM; @@ -597,10 +597,9 @@ gk20a_instmem_new(struct nvkm_device *device, int index, nvkm_info(&imem->base.subdev, "using IOMMU\n"); } else { - init_dma_attrs(&imem->attrs); - dma_set_attr(DMA_ATTR_NON_CONSISTENT, &imem->attrs); - dma_set_attr(DMA_ATTR_WEAK_ORDERING, &imem->attrs); - dma_set_att...

...gt;base.vaddr = dma_alloc_attrs(dev, npages << PAGE_SHIFT, &node->handle, GFP_KERNEL, - &imem->attrs); + imem->attrs); if (!node->base.vaddr) { nvkm_error(subdev, "cannot allocate DMA memory\n"); return -ENOMEM; @@ -597,10 +597,9 @@ gk20a_instmem_new(struct nvkm_device *device, int index, nvkm_info(&imem->base.subdev, "using IOMMU\n"); } else { - init_dma_attrs(&imem->attrs); - dma_set_attr(DMA_ATTR_NON_CONSISTENT, &imem->attrs); - dma_set_attr(DMA_ATTR_WEAK_ORDERING, &imem->attrs); - dma_set_att...

...vaddr) > gk20a_instobj_iommu_recycle_vaddr(node); > > - spin_unlock_irqrestore(&imem->lock, flags); > + mutex_unlock(&imem->lock); > > r = list_first_entry(&node->base.mem.regions, struct nvkm_mm_node, > rl_entry); > @@ -580,7 +577,7 @@ gk20a_instmem_new(struct nvkm_device *device, int index, > if (!(imem = kzalloc(sizeof(*imem), GFP_KERNEL))) > return -ENOMEM; > nvkm_instmem_ctor(&gk20a_instmem, device, index, &imem->base); > - spin_lock_init(&imem->lock); > + mutex_init(&imem->lock); > *pimem =...

After observing random crashes on Tegra devices when patch "fb/gf100: defer DMA mapping of scratch page to oneinit() hook" was applied, I noticed that moving the 100c10 page allocation to the oneinit() hook resulted in that page being now allocated for Tegra as well, and accesses be made to members of gf100_fb which were not accessible because gk20a_fb_new() called nvkm_fb_new_()

...drm/nouveau/nvkm/engine/device/base.c +++ b/drm/nouveau/nvkm/engine/device/base.c @@ -2131,7 +2131,7 @@ nv12b_chipset = { .bar = gk20a_bar_new, .bus = gf100_bus_new, .clk = gm20b_clk_new, - .fb = gk20a_fb_new, + .fb = gm20b_fb_new, .fuse = gm107_fuse_new, .ibus = gk20a_ibus_new, .imem = gk20a_instmem_new, diff --git a/drm/nouveau/nvkm/subdev/fb/Kbuild b/drm/nouveau/nvkm/subdev/fb/Kbuild index edcc157e6ac8..ef47d57fcb87 100644 --- a/drm/nouveau/nvkm/subdev/fb/Kbuild +++ b/drm/nouveau/nvkm/subdev/fb/Kbuild @@ -24,6 +24,7 @@ nvkm-y += nvkm/subdev/fb/gk104.o nvkm-y += nvkm/subdev/fb/gk20a.o nvkm-y +=...

Hello everyone, it seems that GP10B support has regressed recently. With linux-next, I need to modify device/base.c to set .mmu = gp10b_mmu_new for GP10B (makes sense - I guess this was left as gf100_mmu_new as a typo) to probe. After that, running a trivial testcase (running a NOP method in 3D class) fails with [ 110.084649] nouveau 17000000.gpu: fifo: read fault at 0000011000 engine 06

...1..d2d6d5f4028a 100644 > > --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c > > +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c > > @@ -2380,7 +2380,7 @@ nv13b_chipset = { > > .fuse = gm107_fuse_new, > > .ibus = gp10b_ibus_new, > > .imem = gk20a_instmem_new, > > - .ltc = gp102_ltc_new, > > + .ltc = gp10b_ltc_new, > > .mc = gp10b_mc_new, > > .mmu = gp10b_mmu_new, > > .secboot = gp10b_secboot_new, > > diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild...

...t;cpuaddr) { + node->base.vaddr = dma_alloc_attrs(dev, npages << PAGE_SHIFT, + &node->handle, GFP_KERNEL, + &imem->attrs); + if (!node->base.vaddr) { nvkm_error(subdev, "cannot allocate DMA memory\n"); return -ENOMEM; } @@ -611,18 +591,14 @@ gk20a_instmem_new(struct nvkm_device *device, int index, imem->mm = &tdev->iommu.mm; imem->domain = tdev->iommu.domain; imem->iommu_pgshift = tdev->iommu.pgshift; - imem->cpu_map = gk20a_instobj_cpu_map_iommu; imem->iommu_bit = tdev->func->iommu_bit; nvkm_info(&amp...

...t; > --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c > > > +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c > > > @@ -2380,7 +2380,7 @@ nv13b_chipset = { > > > .fuse = gm107_fuse_new, > > > .ibus = gp10b_ibus_new, > > > .imem = gk20a_instmem_new, > > > - .ltc = gp102_ltc_new, > > > + .ltc = gp10b_ltc_new, > > > .mc = gp10b_mc_new, > > > .mmu = gp10b_mmu_new, > > > .secboot = gp10b_secboot_new, > > > diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild b/drivers/gpu/drm/n...

From: Thierry Reding <treding at nvidia.com> Hi, the GPU on Jetson TX2 (GP10B) does not work properly on all devices. Why exactly is not clear, but there are slight differences between the SKUs that were tested. It turns out that the biggest issue is that on some devices (e.g. the one that I have), pulsing the GPU reset twice as is done in the current code (once as part of the power-ungate

These 4 patches fix two issues that existed on Tegra regarding DMA: 1) The bit indicating whether to use an IOMMU or not was hardcoded ; make this a platform property and use it in instmem 2) The DMA mask was not set for platform devices. Fix this by converting more pci_dma* to the DMA API, and use that more generic code to set the DMA mask properly for all platforms. Tested on both x86

...= dma_alloc_attrs(dev, npages << PAGE_SHIFT, > + &node->handle, GFP_KERNEL, > + &imem->attrs); > + if (!node->base.vaddr) { > nvkm_error(subdev, "cannot allocate DMA memory\n"); > return -ENOMEM; > } > @@ -611,18 +591,14 @@ gk20a_instmem_new(struct nvkm_device *device, int index, > imem->mm = &tdev->iommu.mm; > imem->domain = tdev->iommu.domain; > imem->iommu_pgshift = tdev->iommu.pgshift; > - imem->cpu_map = gk20a_instobj_cpu_map_iommu; > imem->iommu_bit = tdev->func->iommu...

Hi, This is fourth approach for replacing struct dma_attrs with unsigned long. The main patch (1/44) doing the change is split into many subpatches for easier review (2-42). They should be squashed together when applying. *Important:* Patchset is tested on my ARM platforms and *only* build tested on allyesconfigs: ARM, ARM64, i386, x86_64 and powerpc. Please kindly provide reviewes and tests

Thanks to Thierry for finding this - applying index e14643615698..00eeaaffeae5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -2369,7 +2369,7 @@ nv13b_chipset = { .imem = gk20a_instmem_new, .ltc = gp100_ltc_new, .mc = gp10b_mc_new, - .mmu = gf100_mmu_new, + .mmu = gp10b_mmu_new, .secboot = gp10b_secboot_new, .pmu = gm20b_pmu_new, .timer = gk20a_timer_new, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp10b.c b/driver...

From: Thierry Reding <treding at nvidia.com> Hi Ben, here's a revised subset of the patches I had sent out a couple of weeks ago. I've reworked the BAR2 accesses in the way that you had suggested, which at least for GP10B turned out to be fairly trivial to do. I have not looked in detail at this for GV11B yet, but a cursory look showed that BAR2 is accessed in more places, so the

From: Thierry Reding <treding at nvidia.com> Hi Ben, here's a revised subset of the patches I had sent out a couple of weeks ago. I've reworked the BAR2 accesses in the way that you had suggested, which at least for GP10B turned out to be fairly trivial to do. I have not looked in detail at this for GV11B yet, but a cursory look showed that BAR2 is accessed in more places, so the