search for: gk20a_bar_oclass

Some BARs (like GK20A's) do not support being ioremapped write-combined. Add a boolean property to the BAR structure and handle that case in the Nouveau BO implementation. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drivers/gpu/drm/nouveau/core/include/subdev/bar.h | 3 +++ drivers/gpu/drm/nouveau/nouveau_bo.c | 17 ++++++++++++----- 2 files changed, 15

...;>>nv50_instmem_oclass; >>> device->oclass[NVDEV_SUBDEV_VM ] = >>>&nvc0_vmmgr_oclass; >>>- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; >>>+ device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass; >>> device->oclass[NVDEV_ENGINE_DMAOBJ ] = >>>&nvd0_dmaeng_oclass; >>> device->oclass[NVDEV_ENGINE_FIFO ] = >>>gk20a_fifo_oclass; >>> device->oclass[NVDEV_ENGINE_SW ] = >>>nvc0_softwa...

...NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; - device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; + device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bar.h b/drivers/gpu/drm/nouveau/core/i...

...t;oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; >> device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; >>- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; >>+ device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass; >> device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; >> device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; >> device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; >>diff --git a/drivers/gpu/dr...

...ice->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; > + device->oclass[NVDEV_SUBDEV_INSTMEM] = gk20a_instmem_oclass; > device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; > device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass; > device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; > diff --git a/nvkm/include/subdev/instmem.h b/nvkm/include/subdev/instmem.h > index c1df26f3230c..6264660bedce 100644 > --- a/nvkm/include/subdev/instmem.h > +++ b/nvkm/include/subdev/instmem.h > @@...

...NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = gk20a_instmem_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; diff --git a/nvkm/include/subdev/instmem.h b/nvkm/include/subdev/instmem.h index c1df26f3230c..6264660bedce 100644 --- a/nvkm/include/subdev/instmem.h +++ b/nvkm/include/subdev/instmem.h @@ -48,5 +48,6 @@ nouveau_instmem(void *obj)...

...[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; + device->oclass[NVDEV_SUBDEV_INSTMEM] = gk20a_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; diff --git a/drm/nouveau/nvkm/subdev/fb/ramgk20a.c b/drm/nouveau/nvkm/subdev/fb/ramgk20a.c index 5f30db1..60d8e1c 100644 --- a/drm/nouveau/nvkm/subdev/fb/ramgk20a.c +++ b/drm/nouveau/nvkm/subdev/fb/ramgk20a.c @@ -23,99 +23,17 @@...

...ce->oclass[NVDEV_SUBDEV_INSTMEM] = gk20a_instmem_oclass; > - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; > + device->oclass[NVDEV_SUBDEV_MMU ] = &gk20a_mmu_oclass; > device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass; > device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; > device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; > diff --git a/drm/nouveau/nvkm/subdev/mmu/Kbuild b/drm/nouveau/nvkm/subdev/mmu/Kbuild > index 012c9db687b2..141302a8e933 10...

Hi, This series includes some pieces of fixes to complete the GK20A power on/off sequences and add the suspend/resume support. The patches 1/11 - 4/11 are based on the linux-next-20141219. The patches 5/11 - 11/11 are based on the branch "linux-3.19" of Ben Skeggs's tree (http://cgit.freedesktop.org/~darktama/nouveau). Thanks, Vince Vince Hsu (4): (linux-next-20141219) ARM:

Hi, Generally the the imported buffers which has memory type TTM_PL_TT are mapped as small pages probably due to lack of big page allocation. But the platform device which also use memory type TTM_PL_TT, like GK20A, can *allocate* big page though the IOMMU hardware inside the SoC. This is a try to map the imported buffers as big pages in GMMU by the platform IOMMU. With some preparation work to

Changes since v3: - Use a single dma_attr for all DMA-API allocations in instmem instead of one per allocation - Use device.info.ram_size instead of pfb->ram to check whether VRAM is present outside of nvkm Changes since v2: - Cleaner changes for ltc - Fixed typos in gk20a instmem IOMMU comments Changes since v1: - Add missing else condition in ltc - Remove extra flags that slipped into

Second version of this patchset. Not many changes since first version - I hope this means the changes are not too controversial. Changes since v1: - Removed lookup for previous FW files in "nouveau/" - Went back to using request_firmware() since we only try to load one file Original cover letter follows: GM20B is the GPU of the upcoming Tegra X1 SoC. This series adds initial support

Hello everyone, GM20B is the GPU of the upcoming Tegra X1 SoC. This series adds initial support for it, based on a rework of the already-supported GK20A. It also introduces support for NVIDIA-provided firmware files, which is why I have added a few NVIDIA people who are relevant to this discussion. The first patch adds support for loading the FECS and GPCCS firmwares from firmware files

Changes since v1: - Add missing else condition in ltc - Remove extra flags that slipped into nouveau_display.c and nv84_fence.c. Original cover letter: Patches 1-3 make the presence of a RAM device optional, and remove GK20A's dummy RAM driver we were using so far. On chips using shared memory, such a device can confuse the driver into moving objects where there is no need to, and can trick

A series I have waited too long to submit, and the recent refactoring made me pay the price of my perfectionism, so here are the features that are at least completed Patches 1-3 make the presence of a RAM device optional, and remove GK20A's dummy RAM driver we were using so far. On chips using shared memory, such a device can confuse the driver into moving objects where there is no need to,

Thanks Ilia for the v2 review! Here is the v3 of this IOMMU support for GK20A series. Changes since v2: - Cleaner changes for ltc - Fixed typos in gk20a instmem IOMMU comments Changes since v1: - Add missing else condition in ltc - Remove extra flags that slipped into nouveau_display.c and nv84_fence.c. Original cover letter: Patches 1-3 make the presence of a RAM device optional, and remove