Displaying 16 results from an estimated 16 matches for "gk208_pmu_new".
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gk104_pmu_new
2015 Dec 21
0
[PATCH] therm: debug print the FSRM config on [nvc0, nvf0) cards
...{
.mxm = nv50_mxm_new,
.pci = g94_pci_new,
.pmu = gk110_pmu_new,
- .therm = gf119_therm_new,
+ .therm = gk110_therm_new,
.timer = nv41_timer_new,
.volt = gk104_volt_new,
.ce[0] = gk104_ce_new,
@@ -1878,7 +1878,7 @@ nv106_chipset = {
.mxm = nv50_mxm_new,
.pci = g94_pci_new,
.pmu = gk208_pmu_new,
- .therm = gf119_therm_new,
+ .therm = gk110_therm_new,
.timer = nv41_timer_new,
.volt = gk104_volt_new,
.ce[0] = gk104_ce_new,
@@ -1914,7 +1914,7 @@ nv108_chipset = {
.mxm = nv50_mxm_new,
.pci = g94_pci_new,
.pmu = gk208_pmu_new,
- .therm = gf119_therm_new,
+ .therm = gk110_therm_new,...
2018 Jan 26
1
[RFC v2 1/4] drm/nouveau: Add support for basic clockgating on Kepler1
...gf119_therm_new,
> + .therm = gk104_therm_new,
> .timer = nv41_timer_new,
> .top = gk104_top_new,
> .volt = gk104_volt_new,
> @@ -1900,7 +1901,7 @@ nv106_chipset = {
> .mxm = nv50_mxm_new,
> .pci = gk104_pci_new,
> .pmu = gk208_pmu_new,
> - .therm = gf119_therm_new,
> + .therm = gk104_therm_new,
> .timer = nv41_timer_new,
> .top = gk104_top_new,
> .volt = gk104_volt_new,
> @@ -1938,7 +1939,7 @@ nv108_chipset = {
> .mxm = nv50_mxm_new,
> .pci = gk104_pci_n...
2018 Jan 26
0
[RFC v2 1/4] drm/nouveau: Add support for basic clockgating on Kepler1
....mxm = nv50_mxm_new,
.pci = gk104_pci_new,
.pmu = gk110_pmu_new,
- .therm = gf119_therm_new,
+ .therm = gk104_therm_new,
.timer = nv41_timer_new,
.top = gk104_top_new,
.volt = gk104_volt_new,
@@ -1900,7 +1901,7 @@ nv106_chipset = {
.mxm = nv50_mxm_new,
.pci = gk104_pci_new,
.pmu = gk208_pmu_new,
- .therm = gf119_therm_new,
+ .therm = gk104_therm_new,
.timer = nv41_timer_new,
.top = gk104_top_new,
.volt = gk104_volt_new,
@@ -1938,7 +1939,7 @@ nv108_chipset = {
.mxm = nv50_mxm_new,
.pci = gk104_pci_new,
.pmu = gk208_pmu_new,
- .therm = gf119_therm_new,
+ .therm = gk104_therm_new...
2018 Jan 26
0
[RFC v3 1/4] drm/nouveau: Add support for basic clockgating on Kepler1
....mxm = nv50_mxm_new,
.pci = gk104_pci_new,
.pmu = gk110_pmu_new,
- .therm = gf119_therm_new,
+ .therm = gk104_therm_new,
.timer = nv41_timer_new,
.top = gk104_top_new,
.volt = gk104_volt_new,
@@ -1900,7 +1901,7 @@ nv106_chipset = {
.mxm = nv50_mxm_new,
.pci = gk104_pci_new,
.pmu = gk208_pmu_new,
- .therm = gf119_therm_new,
+ .therm = gk104_therm_new,
.timer = nv41_timer_new,
.top = gk104_top_new,
.volt = gk104_volt_new,
@@ -1938,7 +1939,7 @@ nv108_chipset = {
.mxm = nv50_mxm_new,
.pci = gk104_pci_new,
.pmu = gk208_pmu_new,
- .therm = gf119_therm_new,
+ .therm = gk104_therm_new...
2018 Jan 15
0
[RFC 1/4] drm/nouveau: Add support for basic clockgating on Kepler1
....mxm = nv50_mxm_new,
.pci = gk104_pci_new,
.pmu = gk110_pmu_new,
- .therm = gf119_therm_new,
+ .therm = gk104_therm_new,
.timer = nv41_timer_new,
.top = gk104_top_new,
.volt = gk104_volt_new,
@@ -1900,7 +1901,7 @@ nv106_chipset = {
.mxm = nv50_mxm_new,
.pci = gk104_pci_new,
.pmu = gk208_pmu_new,
- .therm = gf119_therm_new,
+ .therm = gk104_therm_new,
.timer = nv41_timer_new,
.top = gk104_top_new,
.volt = gk104_volt_new,
@@ -1938,7 +1939,7 @@ nv108_chipset = {
.mxm = nv50_mxm_new,
.pci = gk104_pci_new,
.pmu = gk208_pmu_new,
- .therm = gf119_therm_new,
+ .therm = gk104_therm_new...
2018 Jan 26
6
[RFC v2 0/4] Implement full clockgating for Kepler1 and 2
Next version of my patchseries for adding clockgating support for
kepler1 and 2 on nouveau. The first version of this series can be found
here:
https://patchwork.freedesktop.org/series/36504/
Some minor changes:
- Clarified that SLCG stands for 'secondary level clockgating', thanks
for the small tip nvidia!
- Removed the concept of levels, this was more useful for debugging
then
2018 Jan 15
6
[RFC 0/4] Implement full clockgating for Kepler1 and 2
It's here! After a lot of investigation, rewrites, and traces, I present
the patch series to implement all known levels of clockgating for
Kepler1 and Kepler2 GPUs.
Starting with Fermi GPUs (this is probably present on earlier GPUs as
well, but with a far less easy to manage interface), nvidia added two
clockgating levels that are handled mostly in firmware (with the
exception of course, of
2016 Jan 01
9
[PATCH v4 0/9] PCIe speed changes
overall it is for the most part the same as my older version.
I cleaned up some copyright things, so that it is more like the others.
Also I moved the print about the max speed supported into preinit and did
some other minor cleanups in the 3rd commit.
Happy testing (and performance for prime offloading setups)
Karol Herbst (9):
pci: add gk104 variant
pci: add gf106 variant
pci: implement
2018 Jan 26
6
[RFC v3 0/4] Implement full clockgating for Kepler1 and 2
Next version of my patchseries for adding clockgating support for
kepler1 and 2 on nouveau. The first version of this series can be found
here:
https://patchwork.freedesktop.org/series/36504/
Some very important changes:
- Fix gf100_clkgate_init() to actually write registers! This got broken
in the last version by accident
- Dump the register packs and the resulting register writes into
2018 Jan 29
5
[RFC v4 0/5] Implement full clockgating for Kepler1 and 2
Next version of my patchseries for adding clockgating support for
kepler1 and 2 on nouveau. The first version of this series can be found
here:
https://patchwork.freedesktop.org/series/36504/
One small change:
- Set therm->clkgate_enabled to false until the last patch, where we
introduce the NvPmEnableGating option
Lyude Paul (5):
drm/nouveau: Add support for basic clockgating on
2018 Jan 30
5
[RFC v5 0/5] Implement full clockgating for Kepler1 and 2
Next version of my patchseries for adding clockgating support for
kepler1 and 2 on nouveau. The first version of this series can be found
here:
https://patchwork.freedesktop.org/series/36504/
One small change:
- Add Martin's R-B, whoops
Lyude Paul (5):
drm/nouveau: Add support for basic clockgating on Kepler1
drm/nouveau: Add support for BLCG on Kepler1
drm/nouveau: Add support for
2018 Feb 01
5
[RFC v6 0/5] Implement full clockgating for Kepler1 and 2
Next version of my patchseries for adding clockgating support for
kepler1 and 2 on nouveau. The first version of this series can be found
here:
https://patchwork.freedesktop.org/series/36504/
Some small changes (shouldn't change anything functionally):
- Made gf100_therm_new, gk104_clkgate_pack, and
gk110_fb_clkgate_blcg_init_unk_0 static (re: kbuild test bot)
- Making all three of
2015 Oct 12
12
[PATCH 0/9] PCIe speed changes
this patch series implements PCIe speed changes for Tesla and newer.
The Kepler and Fermi bits are tested on my cards at home.
Karol Herbst (9):
pci: add gk104 variant
pci: add gf106 variant
pci: implement generic code for PCIe speed change
pci: implement pcie speed change for tesla
pci: implement pcie speed change on Fermi
pci: implement PCIe speed change for kepler+
bios/perf:
2015 Oct 13
12
[PATCH v2 0/9] PCIEs speed change
overall the same as the old stuff, but with better namings and tirivialy
improved code here and there
Karol Herbst (9):
pci: add gk104 variant
pci: add gf106 variant
pci: implement generic code for PCIe speed change
pci: implement pcie speed change for tesla
pci: implement pcie speed change on Fermi
pci: implement PCIe speed change for kepler+
bios/perf: parse the pci speed from the
2016 Dec 13
15
[PATCH v2 0/15] Falcon library
This was the first step of the secure boot refactoring - as Ben asked for some
fixes, I now submit it as its own series to make it easier to review (and also
because rebasing secure boot on top of this takes time and I don't want to do
it until this is validated!).
This series attempts to factorize the duplicate falcon-related code into a
single library, using the existing nvkm_falcon
2016 Nov 21
33
[PATCH v4 0/33] Secure Boot refactoring / signed PMU firmware support for GM20B
This revision includes initial signed PMU firmware support for GM20B
(Tegra X1). This PMU code will also be used as a basis for dGPU signed
PMU firmware support.
With the PMU code, the refactoring of secure boot should also make
more sense.
ACR (secure boot) support is now separated by the driver version it
originates from. This separation allows to run any version of the ACR
on any chip,