Displaying 7 results from an estimated 7 matches for "gk104_clk_prog_2".
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gk104_clk_prog
2019 Sep 06
1
[PATCH v3] clk: Restore BYPASS_PLL_CHECK from PLLs
...rn nvkm_clk_ctor(&gf100_clk, device, index, true, &clk->base);
}
diff --git a/drm/nouveau/nvkm/subdev/clk/gk104.c b/drm/nouveau/nvkm/subdev/clk/gk104.c
index 0b37e3da..c9ede404 100644
--- a/drm/nouveau/nvkm/subdev/clk/gk104.c
+++ b/drm/nouveau/nvkm/subdev/clk/gk104.c
@@ -388,6 +388,7 @@ gk104_clk_prog_2(struct gk104_clk *clk, int idx)
struct gk104_clk_info *info = &clk->eng[idx];
struct nvkm_device *device = clk->base.subdev.device;
const u32 addr = 0x137000 + (idx * 0x20);
+ bool bypass_state = false;
nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000000);
nvkm_mask(device, ad...
2019 Sep 09
0
[PATCH v4] clk: Restore BYPASS_PLL_CHECK from PLLs
...rn nvkm_clk_ctor(&gf100_clk, device, index, true, &clk->base);
}
diff --git a/drm/nouveau/nvkm/subdev/clk/gk104.c b/drm/nouveau/nvkm/subdev/clk/gk104.c
index 0b37e3da..de3e00c9 100644
--- a/drm/nouveau/nvkm/subdev/clk/gk104.c
+++ b/drm/nouveau/nvkm/subdev/clk/gk104.c
@@ -388,6 +388,7 @@ gk104_clk_prog_2(struct gk104_clk *clk, int idx)
struct gk104_clk_info *info = &clk->eng[idx];
struct nvkm_device *device = clk->base.subdev.device;
const u32 addr = 0x137000 + (idx * 0x20);
+ bool bypass_state = false;
nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000000);
nvkm_mask(device, ad...
2019 Sep 04
1
[RFC PATCH v2] clk: Remove BYPASS_PLL_CHECK from PLLs
...ble sync mode */
nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000004);
diff --git a/drm/nouveau/nvkm/subdev/clk/gk104.c b/drm/nouveau/nvkm/subdev/clk/gk104.c
index 0b37e3da..22cac304 100644
--- a/drm/nouveau/nvkm/subdev/clk/gk104.c
+++ b/drm/nouveau/nvkm/subdev/clk/gk104.c
@@ -400,7 +400,6 @@ gk104_clk_prog_2(struct gk104_clk *clk, int idx)
if (nvkm_rd32(device, addr + 0x00) & 0x00020000)
break;
);
- nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000010);
/* Enable sync mode */
nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000004);
--
2.21.0
2016 Jun 04
0
[PATCH 1/3] nvkm/clk/gf100+: Clean up PLL locking test
...04, 0x00000004);
}
}
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
index 975c401..b650f0c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
@@ -393,11 +393,20 @@ gk104_clk_prog_2(struct gk104_clk *clk, int idx)
if (info->coef) {
nvkm_wr32(device, addr + 0x04, info->coef);
nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001);
- nvkm_msec(device, 2000,
+
+ /* Test PLL lock */
+ nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000000);
+ if (nvkm_msec(device,...
2019 Sep 04
0
[RFC PATCH] clk: Remove BYPASS_PLL_CHECK from PLLs
...nc mode */
nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000004);
}
diff --git a/drm/nouveau/nvkm/subdev/clk/gk104.c b/drm/nouveau/nvkm/subdev/clk/gk104.c
index 0b37e3da..3a07e032 100644
--- a/drm/nouveau/nvkm/subdev/clk/gk104.c
+++ b/drm/nouveau/nvkm/subdev/clk/gk104.c
@@ -394,14 +394,6 @@ gk104_clk_prog_2(struct gk104_clk *clk, int idx)
nvkm_wr32(device, addr + 0x04, info->coef);
nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001);
- /* Test PLL lock */
- nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000000);
- nvkm_msec(device, 2000,
- if (nvkm_rd32(device, addr + 0x00) & 0x...
2016 Jun 17
1
[PATCH v2 1/2] nvkm/clk/gf100+: Clean up PLL locking test
...04, 0x00000004);
}
}
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
index 975c401..06bc0d2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
@@ -393,11 +393,17 @@ gk104_clk_prog_2(struct gk104_clk *clk, int idx)
if (info->coef) {
nvkm_wr32(device, addr + 0x04, info->coef);
nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001);
+
+ /* Test PLL lock */
+ nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000000);
nvkm_msec(device, 2000,
if (nvkm_rd32(device...
2016 Jun 04
3
PM + Init work
Following a series of three patches, two of which have been sitting in my tree
for a while, the third is the result of some inspection of an NV134 BIOS that
seems to use the 0xaf upcode to upload training patterns. Please test!
Roy
Ps. Sorry they come from yet another e-mail address. My previous provider,
eclipso, actively blocks users of git send-email. Inquiries fall on deaf
ears, hence I