search for: gic

Check for: - uninitialized GIC interface addresses; - non-page aligned GIC interface addresses. Panic in both cases. Also remove the code from GICH and GICC to handle non-page aligned interfaces. Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c in...

In the GIC manual, the number of interrupt lines is computed with the following formula: 32(N + 1) where N is the value retrieved from GICD_TYPER. Signed-off-by: Julien Grall <julien.grall@linaro.org> --- xen/arch/arm/gic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen...

If the vgic needs to inject a virtual irq into the guest, but no free LR registers are available, add the irq to a list and return. Whenever an LR register becomes available we add the queued irq to it and remove it from the list. We use the gic lock to protect the list and the bitmask. Signed-off-by: Stefano...

During context switch is_running is set for the next vcpu before the gic state is actually saved. This leads to possible nasty races when interrupts need to be injected after is_running is set to the next vcpu but before the currently running gic state has been saved from the previous vcpu. Use current instead of is_running to check which one is the currently running v...

Rename the existing gic_dump_info to gic_dump_info_guest reduce confusion. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> --- v2: s/gic_dump_info/gic_dump_info_guest/ --- xen/arch/arm/domain.c | 2 +- xen/arch/arm/gic.c | 77 ++++++++++++++++++++++++++++++++++++++++++++- xen/include/asm-arm/...

Print some useful GIC debug information when arch_dump_domain_info is called (''q'' debug key). Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> --- xen/arch/arm/domain.c | 6 ++++++ xen/arch/arm/gic.c | 27 +++++++++++++++++++++++++++ xen/include/asm-arm/gic.h...

We are currently initializing GIC irq properties (ITARGETSR, IPRIORITYR, and GICD_ICFGR) only in gic_route_irq, that is not called for guest interrupts at all. Move the initialization into a separate function (gic_set_irq_properties) and call it from gic_route_irq_to_guest. Changes in v2: - rebased on 77d3a1db3196b1b5864469f8d3f41...

Hi, This is the fifth version of this patch series. With the Versatile Express TC2, it''s possible to boot only with A7 or A15. If the user choose to boot with only A7, the CPU ID will start at 0x100. As Xen relies on it to set the logical ID and the GIC, it won''t be possible to use Xen with this use case. This patch series is divided in 3 parts: - Patch 1: prepare Xen - Patch 2-4: dissociate logical and gic CPU ID - Patch 5-6: dissociate logical and hardware CPU ID For the moment this patch series only modif...

...r updates this time around. Summary: A == acked, M == modified A xen: arm64: Add 8250 earlyprintk support A xen: arm64: Add Basic Platform support for APM X-Gene Storm. A xen: arm64: Add APM implementor id to processor implementers. M xen: arm: add a quirk to handle platforms with unusual GIC layout A xen: arm: allow platform code to select dom0 event channel irq A xen: arm64: Map xgene PCI memory regions and interrupts to dom0. A xen: arm: include ns16550 driver on arm64 too M xen: arm: Handle cpus nodes with #address-cells > 1 A xen: arm: Make register bit definitions uns...

We need to write the irq number to GICC_DIR on the physical cpu that previously received the interrupt, but currently we are doing it on the pcpu that received the maintenance interrupt. As a consequence if a vcpu is migrated to a different pcpu, the irq is going to be EOI''ed on the wrong pcpu. This covers the case where dom0...

We need to write the irq number to GICC_DIR on the physical cpu that previously received the interrupt, but currently we are doing it on the pcpu that received the maintenance interrupt. As a consequence if a vcpu is migrated to a different pcpu, the irq is going to be EOI''ed on the wrong pcpu. This covers the case where dom0...

This patch series implements SMP boot for arch/arm, as far as getting all CPUs up and running the idle loop. Changes from v1: - moved barriers out of loop in udelay() - dropped broken GIC change in favour of explanatory comment - made the increment of ready_cpus atomic (I couldn''t move the increment to before signalling the next CPU because the PT switch has to happen between them) - Made secondary CPUs come up directly on the idle vcpus'' stacks, avoidi...

...direct.c b/src/launch-direct.c index 20f6471..6450d7e 100644 --- a/src/launch-direct.c +++ b/src/launch-direct.c @@ -382,9 +382,12 @@ launch_direct (guestfs_h *g, void *datav, const char *arg) MACHINE_TYPE "," #endif #ifdef __aarch64__ - "gic-version=host," + "%s" /* gic-version */ #endif "accel=%s", +#ifdef __aarch64__ + has_kvm && !force_tcg ? "gic-version=host," : "", +#endif !force_tcg ?...

...outing is initialized to the wrong register and overwrites interrupt configuration register (ICFGRn). Reported-by: Sander Bogaert <sander.bogaert@elis.ugent.be> Signed-off-by: Julien Grall <julien.grall@linaro.org> --- Changes in v2: - cpumask was already good... --- xen/arch/arm/gic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index d9940ea..177560e 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -280,7 +280,7 @@ static void __init gic_dist_init(void) /* Route all global IRQs to this CPU */...

...Move smp_call_function and on_selected_cpus to common code. Signed-off-by: Julien Grall <julien.grall@citrix.com> Acked-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Keir Fraser <keir@xen.org> --- Changes in V2: - Add copyright header in xen/common/smp.c xen/arch/arm/gic.c | 3 ++ xen/arch/arm/smp.c | 11 ++-- xen/arch/x86/smp.c | 88 ++------------------------------ xen/common/Makefile | 1 + xen/common/smp.c | 112 +++++++++++++++++++++++++++++++++++++++++ xen/include/asm-arm/gic.h | 1 + x...

(moving to xen-devel, xen-arm is for the older PV ARM port) On Tue, 2013-06-25 at 23:59 +0000, Eric Trudeau wrote: > Hi, I am trying to build the XEN tools for our port of XEN to our > Cortex A15-based platform. > > I am using the repo at git://xenbits.xenproject.org/xen.git to > cross-compile the tools into our rootfs. Which branch/changeset are you using? I've heard that

...en: arm: explicitly map 64 bit release address Bug fixes. xen: arm: enable synchronous console while starting secondary CPUs Improves logging in a useful way. Pretty safe. xen: arm: Add debug keyhandler to dump the physical GIC state. Useful debug functionality. Harmless unless you deliberately trigger the particular debug key. xen: arm: improve early memory map readability Cosmetic, but safe. RFC: xen: arm: handle...

See http://www.gossamer-threads.com/lists/xen/devel/297170 for some information on how to get this going. I''ve rebased and addressed the review comments. With this rebase I''ve picked up some patches from Julien which were required to do things properly, so the gic v7 and device blacklisting patches have been changed to use the proper mechanisms. Previously I was able to boot to a panic due to not finding a root filesystem. This seems to have regressed and now it hangs during dom0 boot. I''m not sure why this is but I think it is because I''v...

...ual Machine for unprivileged guests + * + * Based on ARM Ltd. Versatile Express CoreTile Express (single CPU) + * Cortex-A15 MPCore (V2P-CA15) + * + */ + +/dts-v1/; + +/ { + model = "XENVM-4.2"; + compatible = "xen,xenvm-4.2", "xen,xenvm"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { + bootargs = "console=hvc0 root=/dev/xvda"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; +...

These series patch enable Allwinner A31(code name sun6i) support in assemble. with these patches, the cpu 0 of sun6i SOC could successful boot into the c environment. Bamvor Jian Zhang (4): xen/arm: introduce Cortex-A7 support xen/arm: introduce Allwinner sun6i SOC basic support xen/arm: enable early printk for sun6i xen/arm: enable switch to hyper mode for sun6i xen/arch/arm/Rules.mk