Displaying 3 results from an estimated 3 matches for "gi32".
Did you mean:
gdi32
2010 Nov 08
2
[LLVMdev] Creating tablegen patterns for intrinsics with no return value.
...f atom_g_add_noret : SDNode<"AMDILISD::ATOM_G_ADD_NORET", SDTIL_BinAtomNoRet, [SDNPHasChain]>;
Pattern:
def ATOM_G_ADD_NORET : BinAtomNoRet<IL_OP_UAV_ADD,
"_id($id)", atom_g_add_noret>;
I am Lowering INTRINSIC_W_CHAIN to lower from @llvm.amdil.atomic.add.gi32.noret to the correct instruction with the following code sequence.
LowerINTRINSIC_W_CHAIN(...)
{
...
case AMDILIntrinsic::AMDIL_atomic_add_gu32_noret:
IntNo = AMDILISD::ATOM_G_ADD_NORET; break;
...
SDValue Ops[6];
SDValue chain = Op.getOperand(0);
unsigned numNodes = 0;
if (in...
2010 Nov 08
1
[LLVMdev] Creating tablegen patterns for intrinsics with no return value.
...d. I also set let mayStore = 1 and the same issue shows up. I believe the issue is with the ch not being propogated correctly.
I've attached a before and after instruction creation of DAG.dump().
This is the instruction I'm trying to match:
0x8502b88: i32,ch = llvm.AMDIL.atomic.add.gi32.noret 0x8502a78, 0x8502b00, 0x8502280, 0x8502eb8 [ORD=6] [ID=19]
And I generate this instruction:
0x8503160: i32 = AMDILISD::ATOM_G_ADD_NORET 0x8502a78, 0x8502280, 0x8502eb8, 0x8502f40
0x8502a78: <multiple use>
0x8503608: i32,ch = merge_values 0x8503160, 0x8502a78
What I'm trying...
2010 Nov 08
0
[LLVMdev] Creating tablegen patterns for intrinsics with no return value.
...MDILISD::ATOM_G_ADD_NORET", SDTIL_BinAtomNoRet, [SDNPHasChain]>;
>
> Pattern:
> def ATOM_G_ADD_NORET : BinAtomNoRet<IL_OP_UAV_ADD,
> "_id($id)", atom_g_add_noret>;
>
>
> I am Lowering INTRINSIC_W_CHAIN to lower from @llvm.amdil.atomic.add.gi32.noret to the correct instruction with the following code sequence.
>
> LowerINTRINSIC_W_CHAIN(…)
> {
> …
> case AMDILIntrinsic::AMDIL_atomic_add_gu32_noret:
> IntNo = AMDILISD::ATOM_G_ADD_NORET; break;
> …
> SDValue Ops[6];
> SDValue chain = Op.getOpera...