search for: ghdl

Hi, I hope I can ask my question here and get answers, hints about what might be wrong.     Googled, but got no meaningful answer     Asked GHDL developers but it's not a GHDL issue.     Thus, I arrived here     Already many thanks in advance. - System: Linux-Mint 19 - For building of GHDL, LLVM is required. - Went to apt.llvm.org - Browsed down till Ubuntu square and add the LLVM-8 deb and deb-src line for Ubuntu 18.04 as a .list f...

...his case to assembly instructions. I have no experience with LLVM, but it seems to me that if a VHDL simulator use LLVM for its middleend and backend, it would be hard (if not impossible) to exploit the concurrency of the concerned instructions to do further optimizations. I find that the author of GHDL (a free VHDL compiler and simulator that is probably the most mature among the free ones) said once to be interested of modifying GHDL to compile to LLVM (see http://www.ruby-forum.com/topic/155103), but now it doesn't seems that anything concrete was made for this project in this area. Greeti...

...only VHDL to LLVM project that I know of is nvc. [0] I haven't tried it personally and from a cursory look through the source it seems like there is a LLVM backend and a "native" backend (not sure what that means). If you're really crazy you might want to see if you could massage GHDL [1] (VHDL GCC frontend) + DragonEgg [2] (LLVM backend for GCC) to get you LLVM IR. I'm not sure about Python to LLVM. There was Unladen Swallow [3] but that was abandoned a while ago. Cheers, Jevin [0]: https://github.com/nickg/nvc [1]: https://gna.org/projects/ghdl/ [2]: http://dragonegg.ll...

...o assembly instructions. > I have no experience with LLVM, but it seems to me that if a VHDL simulator use LLVM for its middleend and backend, it would be hard (if not impossible) to exploit the concurrency of the concerned instructions to do further optimizations. > I find that the author of GHDL (a free VHDL compiler and simulator that is probably the most mature among the free ones) said once to be interested of modifying GHDL to compile to LLVM (see http://www.ruby-forum.com/topic/155103), but now it doesn't seems that anything concrete was made for this project in this area. > &g...

...ng on it, and today I did a simple implementation of the IDctSlow procedure as a VHDL module. This module run and decode samples correctly, but It consumes a lot of FPGA resources (logic cells, multipliers, etc..) I will optimize this module for area, to get better results. The testbench uses the GHDL tool to simulate and can be download from the svn: http://svn.xiph.org/trunk/theora-fpga/idctslow/ Just run: $make $make run $make compare to see the testbench working and validating the module data output. This IDctSlow implementation was synthesized to the Altera Stratix II FPGA. The report i...

Hi all, Just a stupid question The IDctSlow function on file idct.c has this line : ip[0] = (ogg_int16_t)((_Gd + _Cd ) >> 0); The ip[0] , _Gd and _Cd are of type ogg_int32_t My question is: The result of (_Gd + _Cd) can be a number with more than 16 bits ? (yes, it can be because they are int32, but the algorithm could guarantee something about that... I dont know...) If

...o assembly instructions. > I have no experience with LLVM, but it seems to me that if a VHDL simulator use LLVM for its middleend and backend, it would be hard (if not impossible) to exploit the concurrency of the concerned instructions to do further optimizations. > I find that the author of GHDL (a free VHDL compiler and simulator that is probably the most mature among the free ones) said once to be interested of modifying GHDL to compile to LLVM (see http://www.ruby-forum.com/topic/155103), but now it doesn't seems that anything concrete was made for this project in this area. > &g...