search for: gf119

Commit df8dc97cd17 (drm/nouveau/kms/nv50: use drm core i2c-over-aux algorithm) switched things over to the drm algo. Unfortunately it generates address-only transactions. Prior to GF119, the hardware had no support for such things, and GF119+ the nouveau code did not handle these properly. The result of this bug is that EDID doesn't make it over for DP (and eDP) screens, which in turn wreaks all sorts of havoc. There have been lots of reports on IRC, a few on mailing lists, a...

We assume that each board has 4 heads for GF119+. However this is not necessarily true - in the case of a GP108 board, the register indicated that there were only 2. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101601 Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- I'm not extremely happy about the fact that we hav...

On 07/04/2017 03:06 AM, Ilia Mirkin wrote: > We assume that each board has 4 heads for GF119+. However this is not > necessarily true - in the case of a GP108 board, the register indicated > that there were only 2. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101601 > Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> > --- > > I'm not ex...

...pports pixel clock rates above 165 MHz. Only activate Dual Link mode when it is actual possible. Signed-off-by: Hauke Mehrtens <hauke at hauke-m.de> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- drm/nouveau/nv50_display.c | 8 ++++---- drm/nouveau/nvkm/engine/disp/gf119.c | 2 +- drm/nouveau/nvkm/engine/disp/nv50.c | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drm/nouveau/nv50_display.c b/drm/nouveau/nv50_display.c index c053c50..93bcfdf 100644 --- a/drm/nouveau/nv50_display.c +++ b/drm/nouveau/nv50_display.c @@ -1961,10 +1961,10 @@ nv50_...

https://bugs.freedesktop.org/show_bug.cgi?id=54646 Bug #: 54646 Summary: i2c failure on Quadro NVS 4200M (GF119 (NVD9)) Classification: Unclassified Product: xorg Version: unspecified Platform: Other OS/Version: All Status: NEW Severity: normal Priority: medium Component: Driver/nouveau AssignedTo: nouveau at lists.f...

Fixes broken dp on GF119: Call Trace: ? nvkm_dp_train_drive+0x183/0x2c0 [nouveau] nvkm_dp_acquire+0x4f3/0xcd0 [nouveau] nv50_disp_super_2_2+0x5d/0x470 [nouveau] ? nvkm_devinit_pll_set+0xf/0x20 [nouveau] gf119_disp_super+0x19c/0x2f0 [nouveau] process_one_work+0x193/0x3c0 worker_thread+0x35/0x3b0 k...

...Dual Link mode when it is actual possible. >> >> Signed-off-by: Hauke Mehrtens <hauke at hauke-m.de> >> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> >> --- >> drm/nouveau/nv50_display.c | 8 ++++---- >> drm/nouveau/nvkm/engine/disp/gf119.c | 2 +- >> drm/nouveau/nvkm/engine/disp/nv50.c | 2 +- >> 3 files changed, 6 insertions(+), 6 deletions(-) >> >> diff --git a/drm/nouveau/nv50_display.c b/drm/nouveau/nv50_display.c >> index c053c50..93bcfdf 100644 >> --- a/drm/nouveau/nv50_display.c >>...

On Wed, Feb 07, 2018 at 06:28:42PM +0200, Ville Syrjälä wrote: > On Sun, Feb 04, 2018 at 06:50:45PM -0500, Ilia Mirkin wrote: > > In case anyone's curious about 30bpp framebuffer support, here's the > > current status: > > > > Kernel: > > > > Ben and I have switched the code to using a 256-based LUT for Kepler+, > > and I've also written a

NVIDIA provided the documentation for mp error 0x10, INVALID_ADDR_SPACE, which apparently happens when trying to use an atomic operation on local or shared memory (instead of global memory). Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- drm/nouveau/nvkm/engine/gr/gf100.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drm/nouveau/nvkm/engine/gr/gf100.c

Unfortunately the ABI is a little annoying around almost requiring a 256-entry lut. While that is being worked out, allow proper mapping of colors in 30bpp framebuffers. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- If I bump the gamma size to 1024, then all existing software will start failing since the gamma set ioctl expects the size to match. But xf86-video-nouveau does not

From: Ben Skeggs <bskeggs at redhat.com> [ Upstream commit a0b694d0af21c9993d1a39a75fd814bd48bf7eb4 ] HW has error checks in place which check that pixel depth is explicitly provided on DP, while HDMI has a "default" setting that we use. In multi-display configurations with identical modelines, but different protocols (HDMI + DP, in this case), it was possible for the DP head to

From: Ben Skeggs <bskeggs at redhat.com> [ Upstream commit a0b694d0af21c9993d1a39a75fd814bd48bf7eb4 ] HW has error checks in place which check that pixel depth is explicitly provided on DP, while HDMI has a "default" setting that we use. In multi-display configurations with identical modelines, but different protocols (HDMI + DP, in this case), it was possible for the DP head to

From: Ben Skeggs <bskeggs at redhat.com> [ Upstream commit a0b694d0af21c9993d1a39a75fd814bd48bf7eb4 ] HW has error checks in place which check that pixel depth is explicitly provided on DP, while HDMI has a "default" setting that we use. In multi-display configurations with identical modelines, but different protocols (HDMI + DP, in this case), it was possible for the DP head to

...t-fallthrough for Clang, fix a warning by explicitly adding a break statement instead of letting the code fall through to the next case. Link: https://github.com/KSPP/linux/issues/115 Signed-off-by: Gustavo A. R. Silva <gustavoars at kernel.org> --- drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.c index 0981b02790e2..bb2e71bf537f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm...

...MHz. > Only activate Dual Link mode when it is actual possible. > > Signed-off-by: Hauke Mehrtens <hauke at hauke-m.de> > Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> > --- > drm/nouveau/nv50_display.c | 8 ++++---- > drm/nouveau/nvkm/engine/disp/gf119.c | 2 +- > drm/nouveau/nvkm/engine/disp/nv50.c | 2 +- > 3 files changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drm/nouveau/nv50_display.c b/drm/nouveau/nv50_display.c > index c053c50..93bcfdf 100644 > --- a/drm/nouveau/nv50_display.c > +++ b/drm/nouveau/nv50_disp...

This adds support on GF119:GV100 (exclusive) for CTM (aka CSC). Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- drivers/gpu/drm/nouveau/dispnv50/atom.h | 6 ++ drivers/gpu/drm/nouveau/dispnv50/base907c.c | 65 +++++++++++++++++++++ drivers/gpu/drm/nouveau/dispnv50/wndw.c | 13 +++++ drivers/gpu/drm/...

This is what was done prior to the big refactor in kernel 3.8, and what was done by xf86-video-nv. Experimentally, it seems like there's some sort of issue with the high-res lut to be used there. Tested on G92. This ends up mattering because fbcon/fbdev chooses the C8 fb format for low-vram systems, which can occur with some IGP-based configurations with little "stolen" vram.

...e that best suits its needs. That's already the case -- NVIDIA actually has like 5 different LUT modes on recent chips. https://github.com/envytools/envytools/blob/master/rnndb/display/nv_evo.xml#L25 <value value="0x4" name="INTERPOLATE_1025_UNITY_RANGE" variants="GF119-"/> <value value="0x5" name="INTERPOLATE_1025_XRBIAS_RANGE" variants="GF119-"/> <value value="0x6" name="INTERPOLATE_1025_XVYCC_RANGE" variants="GF119-"/> <value value="0x7" name="INTERPOLATE_257_UNITY...

...ens (2): drm/nouveau: activate dual link TMDS links only when possible drm/nouveau: increase max pixel clock to 225 MHZ for HDMI drivers/gpu/drm/nouveau/nouveau_connector.c | 6 ++++-- drivers/gpu/drm/nouveau/nv50_display.c | 8 ++++---- drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c | 2 +- 4 files changed, 10 insertions(+), 8 deletions(-) -- 2.1.4

This adds support on GF119:GV100 (exclusive) for CTM (aka CSC). Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- v1 -> v2: - ctm -> csc - mark csc.valid = false when there is no ctm property drivers/gpu/drm/nouveau/dispnv50/atom.h | 6 ++ drivers/gpu/drm/nouveau/dispnv50/base907c.c | 65 +++++++...