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Hello, A user on an NVC3 card (GF106) is running into data errors on m2mf (class 0x9039) that we haven't seen before: http://people.freedesktop.org/~imirkin/nvc0-comparison/nvc3-2014-03-17-agashlin/glean/fbo.html http://people.freedesktop.org/~imirkin/nvc0-comparison/nvc3-2014-03-17-agashlin/spec/!OpenGL%201.1/copyteximage%201D.h...

...d-off-by: Karol Herbst <kherbst at redhat.com> > --- > drm/nouveau/nvkm/subdev/pci/g84.c | 9 +++++++++ > drm/nouveau/nvkm/subdev/pci/g92.c | 1 + > drm/nouveau/nvkm/subdev/pci/g94.c | 1 + > drm/nouveau/nvkm/subdev/pci/gf100.c | 1 + > drm/nouveau/nvkm/subdev/pci/gf106.c | 1 + > drm/nouveau/nvkm/subdev/pci/gk104.c | 1 + > drm/nouveau/nvkm/subdev/pci/pcie.c | 14 ++++++++++++++ > drm/nouveau/nvkm/subdev/pci/priv.h | 2 ++ > 8 files changed, 30 insertions(+) > > diff --git a/drm/nouveau/nvkm/subdev/pci/g84.c b/drm/nouveau/nvkm/subdev/pci/g8...

...04: enable dl_mgr safe mode pci/gk104: wait for ltssm idle before changing the link drm/nouveau/nvkm/subdev/pci/g84.c | 9 +++++++++ drm/nouveau/nvkm/subdev/pci/g92.c | 1 + drm/nouveau/nvkm/subdev/pci/g94.c | 1 + drm/nouveau/nvkm/subdev/pci/gf100.c | 1 + drm/nouveau/nvkm/subdev/pci/gf106.c | 1 + drm/nouveau/nvkm/subdev/pci/gk104.c | 11 +++++++++++ drm/nouveau/nvkm/subdev/pci/pcie.c | 14 ++++++++++++++ drm/nouveau/nvkm/subdev/pci/priv.h | 2 ++ 8 files changed, 40 insertions(+) -- 2.21.0

...ev/pci.h | 2 +- drm/nouveau/nvkm/engine/device/base.c | 22 +++++++++++----------- drm/nouveau/nvkm/subdev/pci/Kbuild | 2 +- drm/nouveau/nvkm/subdev/pci/{g94.c => g92.c} | 10 +++++----- drm/nouveau/nvkm/subdev/pci/gf100.c | 2 +- drm/nouveau/nvkm/subdev/pci/gf106.c | 2 +- drm/nouveau/nvkm/subdev/pci/priv.h | 2 +- 7 files changed, 21 insertions(+), 21 deletions(-) rename drm/nouveau/nvkm/subdev/pci/{g94.c => g92.c} (87%) -- 2.11.0.rc2

...31:0 #define NV9039_LINE_COUNT 0x0320 #define NV9039_LINE_COUNT_VALUE 31:0 As far as I can tell, these checks are not GF106-specific, so I'm not sure why the problem is only showing up there. Maybe there is something else unique about the GF106 user's configuration that causes this to be triggered? Thanks, - Andy On Tue, Mar 18, 2014 at 06:44:30AM -0700, Ilia Mirkin wrote: > Hello, > > A user on an...

taken from nvgpu Signed-off-by: Karol Herbst <kherbst at redhat.com> --- drm/nouveau/nvkm/subdev/pci/g84.c | 9 +++++++++ drm/nouveau/nvkm/subdev/pci/g92.c | 1 + drm/nouveau/nvkm/subdev/pci/g94.c | 1 + drm/nouveau/nvkm/subdev/pci/gf100.c | 1 + drm/nouveau/nvkm/subdev/pci/gf106.c | 1 + drm/nouveau/nvkm/subdev/pci/gk104.c | 1 + drm/nouveau/nvkm/subdev/pci/pcie.c | 14 ++++++++++++++ drm/nouveau/nvkm/subdev/pci/priv.h | 2 ++ 8 files changed, 30 insertions(+) diff --git a/drm/nouveau/nvkm/subdev/pci/g84.c b/drm/nouveau/nvkm/subdev/pci/g84.c index 62438d892..353d70d7...

...ed up some copyright things, so that it is more like the others. Also I moved the print about the max speed supported into preinit and did some other minor cleanups in the 3rd commit. Happy testing (and performance for prime offloading setups) Karol Herbst (9): pci: add gk104 variant pci: add gf106 variant pci: implement generic code for PCIe speed change pci: implement pcie speed change for tesla pci: implement pcie speed change on Fermi pci: implement PCIe speed change for kepler+ bios/perf: parse the pci speed from the bios for tesla and newer cards perf: add fields for pci spe...

this patch series implements PCIe speed changes for Tesla and newer. The Kepler and Fermi bits are tested on my cards at home. Karol Herbst (9): pci: add gk104 variant pci: add gf106 variant pci: implement generic code for PCIe speed change pci: implement pcie speed change for tesla pci: implement pcie speed change on Fermi pci: implement PCIe speed change for kepler+ bios/perf: parse the pci speed from the bios for tesla and newer cards perf: add fields for pci spe...

overall the same as the old stuff, but with better namings and tirivialy improved code here and there Karol Herbst (9): pci: add gk104 variant pci: add gf106 variant pci: implement generic code for PCIe speed change pci: implement pcie speed change for tesla pci: implement pcie speed change on Fermi pci: implement PCIe speed change for kepler+ bios/perf: parse the pci speed from the bios for tesla and newer cards perf: add fields for pci spe...

...variety of limitations (e.g., >>>>> cannot handle blocklinear format), and was only in a few Fermi chips, >>>>> as I understand it. >>>> >>>> According to our driver source, GF100, GF104, GF110, GF114, and GF116 >>>> all have it. [So GF106, GF108, GF117, GF119 don't have it.] We've only >>>> had problems reported against GF116... and only for some people. >>> >>> Hmm, some of our internal documentation is inconsistent about whether it >>> applies to GF100, but otherwise what I see matche...

...art of performing the copy. It has a variety of limitations (e.g., >> > cannot handle blocklinear format), and was only in a few Fermi chips, >> > as I understand it. >> >> According to our driver source, GF100, GF104, GF110, GF114, and GF116 >> all have it. [So GF106, GF108, GF117, GF119 don't have it.] We've only >> had problems reported against GF116... and only for some people. > > Hmm, some of our internal documentation is inconsistent about whether it > applies to GF100, but otherwise what I see matches your list. I guess > &quot...

.../subdev/clk/base.c | 2 +- drm/nouveau/nvkm/subdev/pci/base.c | 2 ++ drm/nouveau/nvkm/subdev/pci/g84.c | 8 +++++ drm/nouveau/nvkm/subdev/pci/g92.c | 1 + drm/nouveau/nvkm/subdev/pci/g94.c | 1 + drm/nouveau/nvkm/subdev/pci/gf100.c | 1 + drm/nouveau/nvkm/subdev/pci/gf106.c | 1 + drm/nouveau/nvkm/subdev/pci/gk104.c | 29 +++++++++++++----- drm/nouveau/nvkm/subdev/pci/gp100.c | 11 +++++++ drm/nouveau/nvkm/subdev/pci/pcie.c | 42 +++++++++++++++++++++++--- drm/nouveau/nvkm/subdev/pci/priv.h | 16 ++++++++++ 14 files changed, 112 insertions(+), 13 d...

--- man/nouveau.man | 9 ++++++++- src/nv_driver.c | 8 ++++++-- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/man/nouveau.man b/man/nouveau.man index 07d53c8..4878f24 100644 --- a/man/nouveau.man +++ b/man/nouveau.man @@ -63,7 +63,14 @@ GF100, GF104, GF106, GF108, GF110, GF114, GF116, GF117, GF119 GK104, GK106, GK107, GK110, GK208 .TP 22 .B GeForce GTX 750 -GM107 +GM107, GM108 +.TP 22 +.B GeForce GTX 9XX +GM200, GM204, GM206 +.TP 22 +.B GeForce GTX 10XX +GP102, GP104, GP106, GP107, GP108 + .SH CONFIGURATION DETAILS Please refer to __xconfigfil...

...m/nouveau/core/engine/device/nvc0.c? (and boot without > the MSI disabling.) The switch has already been made for NVC8 in > 0bae1d61c75 -- perhaps there are more "odd" ones. > > -ilia > Fails exactly the same. case 0xc3: device->cname = "GF106"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass; device->oclass[NVDEV_SU...

...the MSI disabling.) The switch has already been made for NVC8 in >>> 0bae1d61c75 -- perhaps there are more "odd" ones. >>> >>> -ilia >>> >> Fails exactly the same. >> case 0xc3: >> device->cname = "GF106"; >> >> device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; >> device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; >> device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass; >>...

...e for performing LZO decompression as > part of performing the copy. It has a variety of limitations (e.g., > cannot handle blocklinear format), and was only in a few Fermi chips, > as I understand it. According to our driver source, GF100, GF104, GF110, GF114, and GF116 all have it. [So GF106, GF108, GF117, GF119 don't have it.] We've only had problems reported against GF116... and only for some people. > > It is probably easiest to just ignore it. You can distinguish this > decompress engine from normal copy engine by looking at the CE capability > register on fal...

Hello, Various HDMI versions enable higher and higher pixel clocks. However individual GPUs are not required to support the maximum pixel clock supported by the spec in order to be compliant. It appears that some GPUs max out at 225MHz while others at 297MHz (while others still, I assume, are limited to 165MHz, esp among the older ones). We've been unable to find this in the VBIOS (I had a

....c? (and boot without >> the MSI disabling.) The switch has already been made for NVC8 in >> 0bae1d61c75 -- perhaps there are more "odd" ones. >> >> -ilia >> > Fails exactly the same. > case 0xc3: > device->cname = "GF106"; > > device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; > device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; > device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass; > device...

...51 +NV40, NV41, NV43, NV44, NV45, C51, MCP61 .TP 22 .B GeForce 7XXX -G70, G71, G72, G73 +G70, G71, G72, G73, MCP67, MCP68, MCP73 +.TP 22 +.B GeForce 8XXX, 9XXX, 2XX, 3XX +G80, G84, G86, G92, G94, G96, G98, G200, GT215, GT216, GT218, MCP77, +MCP79, MCP89 +.TP 22 +.B GeForce 4XX, 5XX +GF100, GF104, GF106, GF108, GF110, GF114, GF116, GF117, GF119 +.TP 22 +.B GeForce 6XX, 7XX +GK104, GK106, GK107, GK110, GK208 +.TP 22 +.B GeForce GTX 750 +GM107 .SH CONFIGURATION DETAILS Please refer to __xconfigfile__(__filemansuffix__) for general configuration @@ -67,6 +80,10 @@ are supported: .BI "Option...

...ch has already been made for NVC8 in >>>> 0bae1d61c75 -- perhaps there are more "odd" ones. >>>> >>>> -ilia >>>> >>> Fails exactly the same. >>> case 0xc3: >>> device->cname = "GF106"; >>> >>> device->oclass[NVDEV_SUBDEV_VBIOS ] = >>> &nouveau_bios_oclass; >>> device->oclass[NVDEV_SUBDEV_GPIO ] = >>> &nv50_gpio_oclass; >>> device->oclass[NVDEV_SUBDEV...