Displaying 5 results from an estimated 5 matches for "gf100_ram_new".
2017 Apr 10
0
[PATCH 02/11] nvkm/ramgf100: Calculate timings
...0x00030020 // 0x00000000 // 0x00000000
+// 0x00020034 // 0x0000000b
+ ram_wr32(fuc, 0x100b0c, 0x00080028);
+ ram_wr32(fuc, 0x611200, 0x00003330);
+ } else {
ram_wr32(fuc, 0x10f200, 0x00ce0000);
ram_wr32(fuc, 0x10f614, 0x60044e77);
ram_wr32(fuc, 0x10f610, 0x60044e77);
@@ -630,7 +670,7 @@ gf100_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram)
struct nvkm_subdev *subdev = &fb->subdev;
struct nvkm_bios *bios = subdev->device->bios;
struct gf100_ram *ram;
- int ret;
+ int i, ret;
if (!(ram = kzalloc(sizeof(*ram), GFP_KERNEL)))
return -ENOMEM;
@@ -663,11 +703,8 @@ gf100_r...
2016 Mar 04
2
[PATCH 0/2] enable memory reclocking on maxwell1
A quick look over the memory reclocking part inside the maxwell mmiotraces
kind of reminded me of the kepler memory reclocking, it looks for most parts
the same.
I didn't do a deep inspection so treat this with great care, but it seems to
work at least on those maxwell gpus this was tested on.
It depends on the PMU fixes for the fuc5 though, otherwise the PMU might not
work as expected and
2017 Apr 10
0
[PATCH 03/11] nvkm/gddr5: MR calculation for timing table v1.0
...m_nsec(fuc, 1000);
- ram_wr32(fuc, 0x10f344, 0x00600228);
+ ram_wr32(fuc, mr[6], 0x00600228);
ram_nsec(fuc, 1000);
- ram_wr32(fuc, 0x10f348, 0x00700000);
+ ram_wr32(fuc, mr[7], 0x00700000);
ram_wr32(fuc, 0x13d8f4, 0x00000000);
ram_wr32(fuc, 0x61c140, 0x09a40000);
@@ -706,11 +713,9 @@ gf100_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram)
for (i = 0; i < 5; i++)
ram->fuc.r_0x10f290[i] = ramfuc_reg(0x10f290 + (i * 4));
- ram->fuc.r_0x10f300 = ramfuc_reg(0x10f300);
- ram->fuc.r_0x10f338 = ramfuc_reg(0x10f338);
- ram->fuc.r_0x10f340 = ramfuc_reg(0x10f340);
- ram->fuc....
2017 Apr 10
11
Preparations for Fermi DRAM clock changes
No, no, these will not implement Fermi reclocking. This set of patches
contains some of the preparatory work that I deem stable enough to
move upstream. Notable changes
- Training pattern upload routines from GK104+ now shared with GT215+
- Timing calculation for Fermi
- GDDR5 MR calculation from VBIOS timing table v1.0. Also useful for that
pesky GT 240.
- A routine to translate a VBIOS init
2017 Apr 10
14
RESEND Preparations for Fermi DRAM clock changes
Two patches went missing as a result of PEBCAK. No v2 marks as nothing
changed really. Just resending for easier enforcement of patch order
in other people's trees. Sorry for the noise.
Original message:
No, no, these will not implement Fermi reclocking. This set of patches
contains some of the preparatory work that I deem stable enough to
move upstream. Notable changes
- Training pattern