Displaying 5 results from an estimated 5 matches for "gf100_ram_calc".
2017 Apr 10
0
[PATCH 02/11] nvkm/ramgf100: Calculate timings
...km_debug(subdev, "Entry: 290: %08x %08x %08x %08x\n",
+ timing[0], timing[1], timing[2], timing[3]);
+ nvkm_debug(subdev, " 2a0: %08x\n",
+ timing[4]);
+ return 0;
+}
+#undef T
+
static void
gf100_ram_train(struct gf100_ramfuc *fuc, u32 magic)
{
@@ -136,10 +176,11 @@ gf100_ram_calc(struct nvkm_ram *base, u32 freq)
struct nvkm_ram_data *next;
u8 ver, hdr, cnt, len, strap;
u32 data;
+ u32 timing[5];
int ref, div, out;
int from, mode;
int N1, M1, P;
- int ret;
+ int i, ret;
next = &ram->base.target;
next->freq = freq;
@@ -179,6 +220,8 @@ gf100_ram_ca...
2017 Apr 10
0
[PATCH 03/11] nvkm/gddr5: MR calculation for timing table v1.0
...uc_reg r_0x10f290[5];
- struct ramfuc_reg r_0x10f300;
- struct ramfuc_reg r_0x10f338;
- struct ramfuc_reg r_0x10f340;
- struct ramfuc_reg r_0x10f344;
- struct ramfuc_reg r_0x10f348;
+ struct ramfuc_reg r_mr[9];
struct ramfuc_reg r_0x10f910;
struct ramfuc_reg r_0x10f914;
@@ -226,6 +222,19 @@ gf100_ram_calc(struct nvkm_ram *base, u32 freq)
if (ret)
return ret;
+ /* Determine ram-specific MR values */
+ for (i = 0; i < 9; i++)
+ ram->base.mr[i] = ram_rd32(fuc, mr[i]);
+
+ switch (ram->base.type) {
+ case NVKM_RAM_TYPE_GDDR5:
+ ret = nvkm_gddr5_calc(&ram->base, false);
+ break;...
2017 Apr 10
0
[PATCH 01/11] nvkm/ramgf100: Get rid of (size, data) pairs for rammap, ramcfg, timing
...+), 18 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c
index 093223d..fffd01a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c
@@ -133,21 +133,22 @@ gf100_ram_calc(struct nvkm_ram *base, u32 freq)
struct nvkm_device *device = subdev->device;
struct nvkm_clk *clk = device->clk;
struct nvkm_bios *bios = device->bios;
- struct nvbios_ramcfg cfg;
- u8 ver, cnt, len, strap;
- struct {
- u32 data;
- u8 size;
- } rammap, ramcfg, timing;
+ struct n...
2017 Apr 10
11
Preparations for Fermi DRAM clock changes
No, no, these will not implement Fermi reclocking. This set of patches
contains some of the preparatory work that I deem stable enough to
move upstream. Notable changes
- Training pattern upload routines from GK104+ now shared with GT215+
- Timing calculation for Fermi
- GDDR5 MR calculation from VBIOS timing table v1.0. Also useful for that
pesky GT 240.
- A routine to translate a VBIOS init
2017 Apr 10
14
RESEND Preparations for Fermi DRAM clock changes
Two patches went missing as a result of PEBCAK. No v2 marks as nothing
changed really. Just resending for easier enforcement of patch order
in other people's trees. Sorry for the noise.
Original message:
No, no, these will not implement Fermi reclocking. This set of patches
contains some of the preparatory work that I deem stable enough to
move upstream. Notable changes
- Training pattern