search for: gf100_pmu_new

...nvkm_device *, int, struct nvkm_volt **); diff --git a/drm/nouveau/nvkm/engine/device/base.c b/drm/nouveau/nvkm/engine/device/base.c index a364efe..528780c 100644 --- a/drm/nouveau/nvkm/engine/device/base.c +++ b/drm/nouveau/nvkm/engine/device/base.c @@ -1357,7 +1357,7 @@ nvc0_chipset = { .pmu = gf100_pmu_new, .therm = gt215_therm_new, .timer = nv41_timer_new, - .volt = nv40_volt_new, + .volt = gf100_volt_new, .ce[0] = gf100_ce_new, .ce[1] = gf100_ce_new, .disp = gt215_disp_new, @@ -1394,7 +1394,7 @@ nvc1_chipset = { .pmu = gf100_pmu_new, .therm = gt215_therm_new, .timer = nv41_timer_new...

...ice/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index b690bc1..d133016 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -1355,7 +1355,7 @@ nvc0_chipset = { .mxm = nv50_mxm_new, .pci = gf100_pci_new, .pmu = gf100_pmu_new, - .therm = gt215_therm_new, + .therm = gf100_therm_new, .timer = nv41_timer_new, .volt = gf100_volt_new, .ce[0] = gf100_ce_new, @@ -1392,7 +1392,7 @@ nvc1_chipset = { .mxm = nv50_mxm_new, .pci = gf106_pci_new, .pmu = gf100_pmu_new, - .therm = gt215_therm_new, + .therm = gf100_therm_new...

...d133016 100644 > > --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c > > +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c > > @@ -1355,7 +1355,7 @@ nvc0_chipset = { > >         .mxm = nv50_mxm_new, > >         .pci = gf100_pci_new, > >         .pmu = gf100_pmu_new, > > -       .therm = gt215_therm_new, > > +       .therm = gf100_therm_new, > >         .timer = nv41_timer_new, > >         .volt = gf100_volt_new, > >         .ce[0] = gf100_ce_new, > > @@ -1392,7 +1392,7 @@ nvc1_chipset = { > >         .mxm = nv50_mxm_n...

...--git a/drm/nouveau/nvkm/engine/device/base.c b/drm/nouveau/nvkm/engine/device/base.c index 7476ac2..7ec9167 100644 --- a/drm/nouveau/nvkm/engine/device/base.c +++ b/drm/nouveau/nvkm/engine/device/base.c @@ -1354,7 +1354,7 @@ nvc0_chipset = { .mxm = nv50_mxm_new, .pci = gf100_pci_new, .pmu = gf100_pmu_new, - .therm = gt215_therm_new, + .therm = gf100_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, .ce[0] = gf100_ce_new, @@ -1390,7 +1390,7 @@ nvc1_chipset = { .mxm = nv50_mxm_new, .pci = g94_pci_new, .pmu = gf100_pmu_new, - .therm = gt215_therm_new, + .therm = gf100_therm_new,...

...ice/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index b690bc1..d133016 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -1355,7 +1355,7 @@ nvc0_chipset = { .mxm = nv50_mxm_new, .pci = gf100_pci_new, .pmu = gf100_pmu_new, - .therm = gt215_therm_new, + .therm = gf100_therm_new, .timer = nv41_timer_new, .volt = gf100_volt_new, .ce[0] = gf100_ce_new, @@ -1392,7 +1392,7 @@ nvc1_chipset = { .mxm = nv50_mxm_new, .pci = gf106_pci_new, .pmu = gf100_pmu_new, - .therm = gt215_therm_new, + .therm = gf100_therm_new...

...ce/base.c > index b690bc1..d133016 100644 > --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c > +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c > @@ -1355,7 +1355,7 @@ nvc0_chipset = { > .mxm = nv50_mxm_new, > .pci = gf100_pci_new, > .pmu = gf100_pmu_new, > - .therm = gt215_therm_new, > + .therm = gf100_therm_new, > .timer = nv41_timer_new, > .volt = gf100_volt_new, > .ce[0] = gf100_ce_new, > @@ -1392,7 +1392,7 @@ nvc1_chipset = { > .mxm = nv50_mxm_new, > .pci = gf106_pci_n...

...vkm/engine/device/base.c > index b690bc1..d133016 100644 > --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c > +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c > @@ -1355,7 +1355,7 @@ nvc0_chipset = { > .mxm = nv50_mxm_new, > .pci = gf100_pci_new, > .pmu = gf100_pmu_new, > - .therm = gt215_therm_new, > + .therm = gf100_therm_new, > .timer = nv41_timer_new, > .volt = gf100_volt_new, > .ce[0] = gf100_ce_new, > @@ -1392,7 +1392,7 @@ nvc1_chipset = { > .mxm = nv50_mxm_new, > .pci = gf106_pci_new, > .pmu = gf100_pmu_new, &gt...

I've splitted my big series between the part which actually fixes the engine reclocking bits and the part handling voltage/clock updates on temperature change, so that the more reviewed parts can be merged in faster. This series fixes a lot of Engine reclocking issues found on Fermi, Kepler and all Maxwell generation GPUs. It does _not_ fix memory reclocking on Fermi. It mostly contains of

overall it is for the most part the same as my older version. I cleaned up some copyright things, so that it is more like the others. Also I moved the print about the max speed supported into preinit and did some other minor cleanups in the 3rd commit. Happy testing (and performance for prime offloading setups) Karol Herbst (9): pci: add gk104 variant pci: add gf106 variant pci: implement

We are slowly getting there! v4 of the series with some realy good improvements, so I am sure this is like 95% done and only needs some proper polishing and proper Reviews! I also added the NvVoltOffsetmV module parameter, so that a user is able to over and !under!-volt the GPU. Overvolting makes sense, when there are still some reclocking issues left, which might be solved by a higher voltage.

this patch series implements PCIe speed changes for Tesla and newer. The Kepler and Fermi bits are tested on my cards at home. Karol Herbst (9): pci: add gk104 variant pci: add gf106 variant pci: implement generic code for PCIe speed change pci: implement pcie speed change for tesla pci: implement pcie speed change on Fermi pci: implement PCIe speed change for kepler+ bios/perf:

overall the same as the old stuff, but with better namings and tirivialy improved code here and there Karol Herbst (9): pci: add gk104 variant pci: add gf106 variant pci: implement generic code for PCIe speed change pci: implement pcie speed change for tesla pci: implement pcie speed change on Fermi pci: implement PCIe speed change for kepler+ bios/perf: parse the pci speed from the

This revision includes initial signed PMU firmware support for GM20B (Tegra X1). This PMU code will also be used as a basis for dGPU signed PMU firmware support. With the PMU code, the refactoring of secure boot should also make more sense. ACR (secure boot) support is now separated by the driver version it originates from. This separation allows to run any version of the ACR on any chip,