Displaying 2 results from an estimated 2 matches for "gf100_ltc_zbc_clear_depth".
2015 Sep 03
3
[PATCH 0/3] New instmem implementation for Tegra
Due to the lack of implicit synchronization between CPU and GPU on Tegra systems
(like what PCI provides for dGPUs), the instmem implementation of GK20A/GM20B
relied on the slow, legacy PRAMIN so that CPU accesses used the same path as
GPU, making sure we see the same data on both ends.
The recent Nouveau refactoring introduced acquire/release functions on instmem
that help us understand the
2015 Sep 03
2
[PATCH 2/3] ltc/gf100: add flush/invalidate functions
...k %lld ns\n", taken);
> +}
> +
> /* TODO: Figure out tag memory details and drop the over-cautious allocation.
> */
> int
> @@ -215,6 +249,8 @@ gf100_ltc = {
> .zbc = 16,
> .zbc_clear_color = gf100_ltc_zbc_clear_color,
> .zbc_clear_depth = gf100_ltc_zbc_clear_depth,
> + .invalidate = gf100_ltc_invalidate,
> + .flush = gf100_ltc_flush,
> };
>
> int
> diff --git a/drm/nouveau/nvkm/subdev/ltc/gk104.c b/drm/nouveau/nvkm/subdev/ltc/gk104.c
> index 839e6b4c597b..b4f6e0034d58 100644
> --- a/drm/nouveau/nvkm/subdev/ltc/gk104.c
&g...