search for: gf100_ltc_invalid

Due to the lack of implicit synchronization between CPU and GPU on Tegra systems (like what PCI provides for dGPUs), the instmem implementation of GK20A/GM20B relied on the slow, legacy PRAMIN so that CPU accesses used the same path as GPU, making sure we see the same data on both ends. The recent Nouveau refactoring introduced acquire/release functions on instmem that help us understand the

...ev/ltc/gf100.c b/drm/nouveau/nvkm/subdev/ltc/gf100.c > index 45ac765b753e..42ae77533865 100644 > --- a/drm/nouveau/nvkm/subdev/ltc/gf100.c > +++ b/drm/nouveau/nvkm/subdev/ltc/gf100.c > @@ -122,6 +122,40 @@ gf100_ltc_intr(struct nvkm_ltc *ltc) > } > } > > +void > +gf100_ltc_invalidate(struct nvkm_ltc *ltc) > +{ > + struct nvkm_device *device = ltc->subdev.device; > + s64 taken; > + > + nvkm_wr32(device, 0x70004, 0x00000001); > + if ((taken = nvkm_msec(device, 2000, I don't suppose you have access to information on more realisti...

...45ac765b753e..42ae77533865 100644 >>> --- a/drm/nouveau/nvkm/subdev/ltc/gf100.c >>> +++ b/drm/nouveau/nvkm/subdev/ltc/gf100.c >>> @@ -122,6 +122,40 @@ gf100_ltc_intr(struct nvkm_ltc *ltc) >>> } >>> } >>> >>> +void >>> +gf100_ltc_invalidate(struct nvkm_ltc *ltc) >>> +{ >>> + struct nvkm_device *device = ltc->subdev.device; >>> + s64 taken; >>> + >>> + nvkm_wr32(device, 0x70004, 0x00000001); >>> + if ((taken = nvkm_msec(device, 2000, >> I don'...

...100.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drm/nouveau/nvkm/subdev/ltc/gf100.c b/drm/nouveau/nvkm/subdev/ltc/gf100.c index fb0de83da13c..c9eb677967a8 100644 --- a/drm/nouveau/nvkm/subdev/ltc/gf100.c +++ b/drm/nouveau/nvkm/subdev/ltc/gf100.c @@ -129,9 +129,7 @@ gf100_ltc_invalidate(struct nvkm_ltc *ltc) s64 taken; nvkm_wr32(device, 0x70004, 0x00000001); - taken = nvkm_wait_msec(device, 2, 0x70004, 0x00000003, 0x00000000); - if (taken < 0) - nvkm_warn(&ltc->subdev, "LTC invalidate timeout\n"); + taken = nvkm_wait_msec(device, 2000, 0x70004, 0x0000...

From: Thierry Reding <treding at nvidia.com> Hi Ben, here's a revised subset of the patches I had sent out a couple of weeks ago. I've reworked the BAR2 accesses in the way that you had suggested, which at least for GP10B turned out to be fairly trivial to do. I have not looked in detail at this for GV11B yet, but a cursory look showed that BAR2 is accessed in more places, so the

From: Thierry Reding <treding at nvidia.com> Hi Ben, here's a revised subset of the patches I had sent out a couple of weeks ago. I've reworked the BAR2 accesses in the way that you had suggested, which at least for GP10B turned out to be fairly trivial to do. I have not looked in detail at this for GV11B yet, but a cursory look showed that BAR2 is accessed in more places, so the

From: Thierry Reding <treding at nvidia.com> Hi, the GPU on Jetson TX2 (GP10B) does not work properly on all devices. Why exactly is not clear, but there are slight differences between the SKUs that were tested. It turns out that the biggest issue is that on some devices (e.g. the one that I have), pulsing the GPU reset twice as is done in the current code (once as part of the power-ungate