search for: gf100_ltc_flush

Due to the lack of implicit synchronization between CPU and GPU on Tegra systems (like what PCI provides for dGPUs), the instmem implementation of GK20A/GM20B relied on the slow, legacy PRAMIN so that CPU accesses used the same path as GPU, making sure we see the same data on both ends. The recent Nouveau refactoring introduced acquire/release functions on instmem that help us understand the

...break; > + )) < 0) > + nvkm_warn(&ltc->subdev, "L2 invalidate timeout\n"); > + > + if (taken > 0) > + nvkm_debug(&ltc->subdev, "LTC invalidate took %lld ns\n", taken); > +} > + > +void > +gf100_ltc_flush(struct nvkm_ltc *ltc) > +{ > + struct nvkm_device *device = ltc->subdev.device; > + s64 taken; > + > + nvkm_wr32(device, 0x70010, 0x00000001); > + if ((taken = nvkm_msec(device, 2000, > + if ((nvkm_rd32(device, 0x70010) & 0x00000003)...

...000); - if (taken < 0) - nvkm_warn(&ltc->subdev, "LTC invalidate timeout\n"); + taken = nvkm_wait_msec(device, 2000, 0x70004, 0x00000003, 0x00000000); if (taken > 0) nvkm_debug(&ltc->subdev, "LTC invalidate took %lld ns\n", taken); @@ -144,9 +142,7 @@ gf100_ltc_flush(struct nvkm_ltc *ltc) s64 taken; nvkm_wr32(device, 0x70010, 0x00000001); - taken = nvkm_wait_msec(device, 2, 0x70010, 0x00000003, 0x00000000); - if (taken < 0) - nvkm_warn(&ltc->subdev, "LTC flush timeout\n"); + taken = nvkm_wait_msec(device, 2000, 0x70010, 0x00000003, 0x...

..., u32 addr, u32 size, u32 pitch, u32 flags, struct nvkm_fb_tile *); diff --git a/drm/nouveau/nvkm/subdev/ltc/priv.h b/drm/nouveau/nvkm/subdev/ltc/priv.h index 8b95f96e..4af4aebe 100644 --- a/drm/nouveau/nvkm/subdev/ltc/priv.h +++ b/drm/nouveau/nvkm/subdev/ltc/priv.h @@ -35,7 +35,7 @@ void gf100_ltc_flush(struct nvkm_ltc *); extern const struct nvkm_bitfield gf100_ltc_lts_intr_name[]; void gm107_ltc_intr(struct nvkm_ltc *); -void gm107_ltc_intr_lts(struct nvkm_ltc *, int ltc, int lts); +void gm107_ltc_intr_lts(struct nvkm_ltc *ltc, int c, int s); void gm107_ltc_cbc_clear(struct nvkm_ltc *, u32,...

From: Thierry Reding <treding at nvidia.com> Hi Ben, here's a revised subset of the patches I had sent out a couple of weeks ago. I've reworked the BAR2 accesses in the way that you had suggested, which at least for GP10B turned out to be fairly trivial to do. I have not looked in detail at this for GV11B yet, but a cursory look showed that BAR2 is accessed in more places, so the

From: Thierry Reding <treding at nvidia.com> Hi Ben, here's a revised subset of the patches I had sent out a couple of weeks ago. I've reworked the BAR2 accesses in the way that you had suggested, which at least for GP10B turned out to be fairly trivial to do. I have not looked in detail at this for GV11B yet, but a cursory look showed that BAR2 is accessed in more places, so the

From: Thierry Reding <treding at nvidia.com> Hi, the GPU on Jetson TX2 (GP10B) does not work properly on all devices. Why exactly is not clear, but there are slight differences between the SKUs that were tested. It turns out that the biggest issue is that on some devices (e.g. the one that I have), pulsing the GPU reset twice as is done in the current code (once as part of the power-ungate