search for: gf100_gr_ctor_fw

...drm/nouveau/nvkm/engine/gr/gf100.c > index ca11ddb..39d482f 100644 > --- a/drm/nouveau/nvkm/engine/gr/gf100.c > +++ b/drm/nouveau/nvkm/engine/gr/gf100.c > @@ -1544,26 +1544,62 @@ gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc) > fuc->data = NULL; > } > > +/** > + * gf100_gr_ctor_fw - helper for loading external GR firmwares > + * > + * A firmware can either be officially provided by NVIDIA (in which case it will > + * use a "NVIDIA name", or be extracted from the binary blob (and use a > + * "Nouveau name". The fwname and nvfwname are to be giv...

Hello everyone, GM20B is the GPU of the upcoming Tegra X1 SoC. This series adds initial support for it, based on a rework of the already-supported GK20A. It also introduces support for NVIDIA-provided firmware files, which is why I have added a few NVIDIA people who are relevant to this discussion. The first patch adds support for loading the FECS and GPCCS firmwares from firmware files

...vers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -1805,6 +1805,7 @@ gf100_gr_new_(const struct gf100_gr_func *func, struct nvkm_device *device,      return ret;      if (gr->firmware) { +          nvkm_info(&gr->base.engine.subdev, "using external firmware\n");                if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) ||             gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) ||             gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) || -- 2.7.3 -------------- next part -------------- An HTML attachment was scrubbed... U...

...km/engine/gr/gf100.c b/drm/nouveau/nvkm/engine/gr/gf100.c >> index 157919c788e6..9e65adbab21c 100644 >> --- a/drm/nouveau/nvkm/engine/gr/gf100.c >> +++ b/drm/nouveau/nvkm/engine/gr/gf100.c >> @@ -1756,24 +1756,70 @@ gf100_gr_ = { >> }; >> >> int >> +gf100_gr_ctor_fw_legacy(struct gf100_gr *gr, const char *fwname, >> + struct gf100_gr_fuc *fuc) >> +{ >> + struct nvkm_subdev *subdev = &gr->base.engine.subdev; >> + struct nvkm_device *device = subdev->device; >> + const struct firmwar...

...ine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -1805,6 +1805,7 @@ gf100_gr_new_(const struct gf100_gr_func *func, struct nvkm_device *device, return ret; if (gr->firmware) { + nvkm_info(&gr->base.engine.subdev, "using external firmware\n"); if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) || gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) || gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) || -- 2.7.3

New version of the secure boot code that works with the blobs just merged into linux-firmware. Since the required Mesa patches are also merged, this set is the last piece of the puzzle to get out-of-the-box accelerated Maxwell 2. The basic code remains the same, with a few improvements with respect to how secure falcons are started. Hopefully the patchset is better split too. I have a

...changed, 51 insertions(+), 5 deletions(-) diff --git a/drm/nouveau/nvkm/engine/gr/gf100.c b/drm/nouveau/nvkm/engine/gr/gf100.c index 157919c788e6..9e65adbab21c 100644 --- a/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drm/nouveau/nvkm/engine/gr/gf100.c @@ -1756,24 +1756,70 @@ gf100_gr_ = { }; int +gf100_gr_ctor_fw_legacy(struct gf100_gr *gr, const char *fwname, + struct gf100_gr_fuc *fuc) +{ + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_device *device = subdev->device; + const struct firmware *fw; + char f[32]; + int ret; + + snprintf(f, sizeof(f), "nouveau/nv%02x_%s&...

...changed, 49 insertions(+), 4 deletions(-) diff --git a/drm/nouveau/nvkm/engine/gr/gf100.c b/drm/nouveau/nvkm/engine/gr/gf100.c index eccdee04107d..ed45f923442f 100644 --- a/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drm/nouveau/nvkm/engine/gr/gf100.c @@ -1756,6 +1756,53 @@ gf100_gr_ = { }; int +gf100_gr_ctor_fw_legacy(struct gf100_gr *gr, const char *fwname, + struct gf100_gr_fuc *fuc, int ret) +{ + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_device *device = subdev->device; + const struct firmware *fw; + char f[32]; + + /* see if this firmware has a legacy path */ + if...

Second version of this patchset. Not many changes since first version - I hope this means the changes are not too controversial. Changes since v1: - Removed lookup for previous FW files in "nouveau/" - Went back to using request_firmware() since we only try to load one file Original cover letter follows: GM20B is the GPU of the upcoming Tegra X1 SoC. This series adds initial support

...gt; diff --git a/drm/nouveau/nvkm/engine/gr/gf100.c b/drm/nouveau/nvkm/engine/gr/gf100.c > index eccdee04107d..ed45f923442f 100644 > --- a/drm/nouveau/nvkm/engine/gr/gf100.c > +++ b/drm/nouveau/nvkm/engine/gr/gf100.c > @@ -1756,6 +1756,53 @@ gf100_gr_ = { > }; > > int > +gf100_gr_ctor_fw_legacy(struct gf100_gr *gr, const char *fwname, > + struct gf100_gr_fuc *fuc, int ret) > +{ > + struct nvkm_subdev *subdev = &gr->base.engine.subdev; > + struct nvkm_device *device = subdev->device; > + const struct firmware *fw; > + char f[32]; > + > + /* see if...

...> diff --git a/drm/nouveau/nvkm/engine/gr/gf100.c b/drm/nouveau/nvkm/engine/gr/gf100.c > index 157919c788e6..9e65adbab21c 100644 > --- a/drm/nouveau/nvkm/engine/gr/gf100.c > +++ b/drm/nouveau/nvkm/engine/gr/gf100.c > @@ -1756,24 +1756,70 @@ gf100_gr_ = { > }; > > int > +gf100_gr_ctor_fw_legacy(struct gf100_gr *gr, const char *fwname, > + struct gf100_gr_fuc *fuc) > +{ > + struct nvkm_subdev *subdev = &gr->base.engine.subdev; > + struct nvkm_device *device = subdev->device; > + const struct firmware *fw; > +...

...au/nvkm/engine/gr/gf100.c >>> index 157919c788e6..9e65adbab21c 100644 >>> --- a/drm/nouveau/nvkm/engine/gr/gf100.c >>> +++ b/drm/nouveau/nvkm/engine/gr/gf100.c >>> @@ -1756,24 +1756,70 @@ gf100_gr_ = { >>> }; >>> >>> int >>> +gf100_gr_ctor_fw_legacy(struct gf100_gr *gr, const char *fwname, >>> + struct gf100_gr_fuc *fuc) >>> +{ >>> + struct nvkm_subdev *subdev = &gr->base.engine.subdev; >>> + struct nvkm_device *device = subdev->device; >>> +...

This is a highly changed revision of the first patch series that adds secure boot support to Nouveau. This code still depends on NVIDIA releasing official firmware files, but the files released with SHIELD TV and Pixel C can already be used on a Jetson TX1. As you know we are working hard to release the official firmware files, however in the meantime it doesn't hurt to review the code so it

This patchset centralizes the firmware-loading procedure to one set of functions instead of having each engine load its firmware as it pleases. This helps ensure that all firmware comes from the same place, namely nvidia/<chip>/. This changes where the firmware is fetched from for falcon/xtensa/bios, but these locations never seemed to have been official anyway. Also for most (all?) chips

This was the first step of the secure boot refactoring - as Ben asked for some fixes, I now submit it as its own series to make it easier to review (and also because rebasing secure boot on top of this takes time and I don't want to do it until this is validated!). This series attempts to factorize the duplicate falcon-related code into a single library, using the existing nvkm_falcon

Hi everyone, Apologies for the big patchset. This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This revision includes initial signed PMU firmware support for GM20B (Tegra X1). This PMU code will also be used as a basis for dGPU signed PMU firmware support. With the PMU code, the refactoring of secure boot should also make more sense. ACR (secure boot) support is now separated by the driver version it originates from. This separation allows to run any version of the ACR on any chip,