Displaying 4 results from an estimated 4 matches for "gf100_clkgate_set".
2017 Apr 26
1
[PATCH] drm/nouveau: Add support for clockgating on Fermi+
...case NVKM_ENGINE_CE1: return 0x14;
> > + case NVKM_ENGINE_MSENC: return 0x18;
> > + case NVKM_ENGINE_CE2: return 0x1c;
> > + default: return -1;
> > + }
> > +}
> > +
> > +void
> > +gf100_clkgate_set(struct nvkm_therm *therm, int gate_idx, bool
> > enable)
> > +{
> > + u8 data;
> > +
> > + if (enable) /* ENG_CLK=auto, BLK_CLK=auto, ENG_PWR=run,
> > BLK_PWR=auto */
> > + data = 0x45;
> > + else /* ENG_CLK=run,...
2017 Apr 25
0
[PATCH] drm/nouveau: Add support for clockgating on Fermi+
...0: return 0x10;
> + case NVKM_ENGINE_CE1: return 0x14;
> + case NVKM_ENGINE_MSENC: return 0x18;
> + case NVKM_ENGINE_CE2: return 0x1c;
> + default: return -1;
> + }
> +}
> +
> +void
> +gf100_clkgate_set(struct nvkm_therm *therm, int gate_idx, bool enable)
> +{
> + u8 data;
> +
> + if (enable) /* ENG_CLK=auto, BLK_CLK=auto, ENG_PWR=run, BLK_PWR=auto */
> + data = 0x45;
> + else /* ENG_CLK=run, BLK_CLK=run, ENG_PWR=run, BLK_PWR=run */
> +...
2017 Apr 25
6
[PATCH] drm/nouveau: Add support for clockgating on Fermi+
...case NVKM_ENGINE_MSPPP: return 0x08;
+ case NVKM_ENGINE_MSVLD: return 0x0c;
+ case NVKM_ENGINE_CE0: return 0x10;
+ case NVKM_ENGINE_CE1: return 0x14;
+ case NVKM_ENGINE_MSENC: return 0x18;
+ case NVKM_ENGINE_CE2: return 0x1c;
+ default: return -1;
+ }
+}
+
+void
+gf100_clkgate_set(struct nvkm_therm *therm, int gate_idx, bool enable)
+{
+ u8 data;
+
+ if (enable) /* ENG_CLK=auto, BLK_CLK=auto, ENG_PWR=run, BLK_PWR=auto */
+ data = 0x45;
+ else /* ENG_CLK=run, BLK_CLK=run, ENG_PWR=run, BLK_PWR=run */
+ data = 0x0;
+
+ nvkm_mask(therm->subdev.device, 0x20200 + gate_...
2017 Apr 25
0
[PATCH] drm/nouveau: Add support for clockgating on Fermi+
...KM_ENGINE_MSVLD: return 0x0c;
> + case NVKM_ENGINE_CE0: return 0x10;
> + case NVKM_ENGINE_CE1: return 0x14;
> + case NVKM_ENGINE_MSENC: return 0x18;
> + case NVKM_ENGINE_CE2: return 0x1c;
> + default: return -1;
> + }
> +}
> +
> +void
> +gf100_clkgate_set(struct nvkm_therm *therm, int gate_idx, bool enable)
> +{
> + u8 data;
> +
> + if (enable) /* ENG_CLK=auto, BLK_CLK=auto, ENG_PWR=run, BLK_PWR=auto */
> + data = 0x45;
> + else /* ENG_CLK=run, BLK_CLK=run, ENG_PWR=run, BLK_PWR=run */
> + data = 0x0;
> +
> + nvkm_...