search for: getx86regnum

...ful or not. But > perhaps we can default most targets to it? > > I prefer not giving a default implementation and aborting with a message that says the target did not implement it. This way we know why it's not working. Is it OK? >> // >> -unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) const { >> +unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) { >> > > What happened to "const"? > I made the function static. >> + unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, >> Is64BitMode); >> + if...

...- } > } > > #endif > Index: lib/Target/X86/X86RegisterInfo.cpp > =================================================================== > --- lib/Target/X86/X86RegisterInfo.cpp (revision 49716) > +++ lib/Target/X86/X86RegisterInfo.cpp (working copy) > @@ -84,7 +84,7 @@ > // getX86RegNum - This function maps LLVM register identifiers to > their X86 > // specific numbering, which is used in various places encoding > instructions. > // > -unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) const { > +unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) { W...

OK, here's a new patch that adds the infrastructure and the implementation for X86, ARM and PPC of GetInstSize and GetFunctionSize. Both functions are virtual functions defined in TargetInstrInfo.h. For X86, I moved some commodity functions from X86CodeEmitter to X86InstrInfo. What do you think? Nicolas Evan Cheng wrote: > > I think both of these belong to TargetInstrInfo. And

...> >> > > I prefer not giving a default implementation and aborting with a > message > that says the target did not implement it. This way we know why it's > not > working. Is it OK? That's ok. > > >>> // >>> -unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) const { >>> +unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) { >>> >> >> What happened to "const"? >> > > I made the function static. Ok. > > >>> + unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC,...

...odeEmitter.cpp. Here NumOps=3 (all registers). and CurOp is 1st initialized to 0. then, the following code gets executed; case X86II::MRMDestReg: { EmitByte(BaseOpcode, CurByte, OS); unsigned SrcRegNum = CurOp + 1; //SrcRegNum=1 EmitRegModRMByte(MI.getOperand(CurOp), GetX86RegNum(MI.getOperand(SrcRegNum)), CurByte, OS); CurOp = SrcRegNum + 1; break; } so here CurOp becomes 2. After this; it comes to; else { // If there is a remaining operand, it must be a trailing immediate. Emit it // according to the right size for the instruction. Some instructions...

On Dec 15, 2007, at 2:15 AM, Duncan Sands wrote: > Can you please paste the line (line number 5305 isn't in > LowerTRAMPOLINE > in my tree...). You have to run svn update for it to have that line... :-) unsigned char N86Reg = ((X86RegisterInfo&)RegInfo).getX86RegNum(NestReg); I've not thought long or hard about the validity of the warning... I'm hoping that it is accurate. Let me know if you think otherwise.

...etDesc/X86MCCodeEmitter.cpp index 7952607..12a30cf 100644 --- a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp +++ b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp @@ -402,6 +402,56 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op, unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U; + // 16-bit addressing forms of the ModR/M byte have a different encoding for + // the R/M field and are far more limited in which registers can be used. + if (Is16BitMemOperand(MI, Op)) { + if (BaseReg) { + // See Table 2-1 "16-Bit Addressing Forms with the ModR/M by...

...alized to 0. >> >> then, the following code gets executed; >> >> case X86II::MRMDestReg: { >> EmitByte(BaseOpcode, CurByte, OS); >> unsigned SrcRegNum = CurOp + 1; //SrcRegNum=1 >> EmitRegModRMByte(MI.getOperand(CurOp), >> GetX86RegNum(MI.getOperand(SrcRegNum)), CurByte, >> OS); >> CurOp = SrcRegNum + 1; >> break; >> } >> so here CurOp becomes 2. >> >> After this; >> >> it comes to; >> else { >> // If there is a remaining operand, it must be a trailin...

...index 7952607..12a30cf 100644 > --- a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp > +++ b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp > @@ -402,6 +402,56 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst > &MI, unsigned Op, > > unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U; > > + // 16-bit addressing forms of the ModR/M byte have a different encoding > for > + // the R/M field and are far more limited in which registers can be > used. > + if (Is16BitMemOperand(MI, Op)) { > + if (BaseReg) { > + // See Table 2-1 "16-B...

...ng code gets executed; >>>> >>>> case X86II::MRMDestReg: { >>>> EmitByte(BaseOpcode, CurByte, OS); >>>> unsigned SrcRegNum = CurOp + 1; //SrcRegNum=1 >>>> EmitRegModRMByte(MI.getOperand(CurOp), >>>> GetX86RegNum(MI.getOperand(SrcRegNum)), CurByte, >>>> OS); >>>> CurOp = SrcRegNum + 1; >>>> break; >>>> } >>>> so here CurOp becomes 2. >>>> >>>> After this; >>>> >>>> it comes to; >>>&...

...>>>>>> case X86II::MRMDestReg: { >>>>>> EmitByte(BaseOpcode, CurByte, OS); >>>>>> unsigned SrcRegNum = CurOp + 1; //SrcRegNum=1 >>>>>> EmitRegModRMByte(MI.getOperand(CurOp), >>>>>> GetX86RegNum(MI.getOperand(SrcRegNum)), >>>>>> CurByte, OS); >>>>>> CurOp = SrcRegNum + 1; >>>>>> break; >>>>>> } >>>>>> so here CurOp becomes 2. >>>>>> >>>>>> After this; >...

...6II::MRMDestReg: { >>>>>>>> EmitByte(BaseOpcode, CurByte, OS); >>>>>>>> unsigned SrcRegNum = CurOp + 1; //SrcRegNum=1 >>>>>>>> EmitRegModRMByte(MI.getOperand(CurOp), >>>>>>>> GetX86RegNum(MI.getOperand(SrcRegNum)), >>>>>>>> CurByte, OS); >>>>>>>> CurOp = SrcRegNum + 1; >>>>>>>> break; >>>>>>>> } >>>>>>>> so here CurOp becomes 2. >>>>>>&g...

...gt;>>>>>> EmitByte(BaseOpcode, CurByte, OS); >>>>>>>>>> unsigned SrcRegNum = CurOp + 1; //SrcRegNum=1 >>>>>>>>>> EmitRegModRMByte(MI.getOperand(CurOp), >>>>>>>>>> GetX86RegNum(MI.getOperand(SrcRegNum)), >>>>>>>>>> CurByte, OS); >>>>>>>>>> CurOp = SrcRegNum + 1; >>>>>>>>>> break; >>>>>>>>>> } >>>>>>>>>> so here Cur...

/Volumes/mrs5/net/llvm/llvm/llvm/lib/Target/X86/X86ISelLowering.cpp: In member function 'llvm::SDOperand llvm::X86TargetLowering::LowerTRAMPOLINE(llvm::SDOperand, llvm::SelectionDAG&)': /Volumes/mrs5/net/llvm/llvm/llvm/lib/Target/X86/X86ISelLowering.cpp: 5305: warning: dereferencing type-punned pointer will break strict- aliasing rules :-(

On Saturday 15 December 2007 08:36:02 Mike Stump wrote: > /Volumes/mrs5/net/llvm/llvm/llvm/lib/Target/X86/X86ISelLowering.cpp: > In member function 'llvm::SDOperand > llvm::X86TargetLowering::LowerTRAMPOLINE(llvm::SDOperand, > llvm::SelectionDAG&)': > /Volumes/mrs5/net/llvm/llvm/llvm/lib/Target/X86/X86ISelLowering.cpp: > 5305: warning: dereferencing type-punned

...gt; EmitByte(BaseOpcode, CurByte, OS); >>>>>>>>>>>> unsigned SrcRegNum = CurOp + 1; //SrcRegNum=1 >>>>>>>>>>>> EmitRegModRMByte(MI.getOperand(CurOp), >>>>>>>>>>>> GetX86RegNum(MI.getOperand(SrcRegNum)), >>>>>>>>>>>> CurByte, OS); >>>>>>>>>>>> CurOp = SrcRegNum + 1; >>>>>>>>>>>> break; >>>>>>>>>>>> } >>>>>...

...ation and aborting with a >> message >> that says the target did not implement it. This way we know why it's >> not >> working. Is it OK? >> > > That's ok. > > >> >>>> // >>>> -unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) const { >>>> +unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) { >>>> >>>> >>> What happened to "const"? >>> >>> >> I made the function static. >> > > Ok. > >...