Displaying 1 result from an estimated 1 matches for "getwriteprocresbegin".
2014 Feb 18
2
[LLVMdev] Question about per-operand machine model
...ALU1]> { let Latency = 1; }
def WriteALU2: SchedWriteRes<[ALU2]> { let Latency = 2; }
def : ItinRW<[WriteALU1, WriteALU2], [II_TEST]>
From this example, we can access the latency information of MI with
'getWriteLatencyEntry()' and the resource information of MI with
'getWriteProcResBegin()'. At this point, I would like to find the
related resource information with each latency information. But TableGen
generates the 'WriteResourceID' of 'MCWriteLatencyEntry' when the
'Write' is referenced by a 'ReadAdvance'. And the order of each
information,...