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Sorry to ask again, but I still can't get it right. The following code compiles and runs, but produces no instructions: Ops.push_back(DAG.getRegister(X86::EAX, MVT::i32)); Ops.push_back(DAG.getConstant(1, MVT::i32)); DAG.getNode(ISD::ADD, DAG.getVTList(MVT::i32), &Ops[0], Ops.size()); I reckon that has something to do with the fact that I am not using the Chain object. But as soon as I try to chain that node, llc tells me that I have the wrong number of operands: Ops.push_back(Chain); Ops.push_back(DAG.getRegister(X86::EAX, MVT::i32));...

Hi, I'm not sure. But in your lowered DAG the chain nodes are the first operands for you custom nodes, however for the other nodes the chain is the last operand. I seem to remember that during targetlowering the chain is the first operand and then it seems to switch over after ISelDAG, this confused me and may have something to do with the issue that you are seeing. I really don't

...debugger behaving correctly. Is that the correct approach? Are there any other suggestions? 02367 /// getNode - Gets or creates the specified node. 02368 /// 02369 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT) { 02370 FoldingSetNodeID ID; 02371 AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0); 02372 void *IP = 0; 02373 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 02374 return SDValue(E, 0); 02375 02376 SDNode *N = new (NodeAllocator) SDNode(Opcode, DL, getVTList(VT)); 02377 CSEMap.InsertNode(N, IP); 02378 02379 AllNodes.push_back(N); 02380 #ifndef NDEBU...

...ying to modify the X86TargetLowering::LowerCALL method by inserting additional instructions before the call. As far as I understand, nodes are created by calling the getNode method on the DAG. If, for example, I insert the following code Ops.push_back(Chain); Chain = DAG.getNode(ISD::TRAP, DAG.getVTList(MVT::Other), &Ops[0], Ops.size()); then an X86 instruction (namely ud2) appears in the output files compiled by llc. So, is my understanding correct that 1) the Chain determines the ordering of the nodes? 2) the second parameter is a set of return types, i. e. in my example, MVT::Other says th...

...htchi wrote: > > Sorry to ask again, but I still can't get it right. > > The following code compiles and runs, but produces no instructions: > Ops.push_back(DAG.getRegister(X86::EAX, MVT::i32)); > Ops.push_back(DAG.getConstant(1, MVT::i32)); > DAG.getNode(ISD::ADD, DAG.getVTList(MVT::i32), &Ops[0], Ops.size()); To read the value of a physical register, a CopyFromReg node is needed. > > I reckon that has something to do with the fact that I am not using > the > Chain object. But as soon as I try to chain that node, llc tells me > that I > have th...

...; opsRes; opsRes.push_back(SDValue(vloadSpecial, 0)); opsRes.push_back(extSym); // Creating an SDNode MDNode<null> (MetaData) with a ch out port SDNode *mdNodeSDNode = CurDAG->getNode(ISD::MDNODE_SDNODE, DL, CurDAG->getVTList(MVT::Other)).getNode(); opsRes.push_back(SDValue(mdNodeSDNode, 0)); SDValue targetConstant = CurDAG->getTargetConstant(1, DL, MVT::i64); SDNode *targetConstantSDNode = targetConstant.getNode(); opsRes.push_back(SDValue(targetConstantSDNode, 0)); S...

...erCALL > method by > inserting additional instructions before the call. > As far as I understand, nodes are created by calling the getNode > method on > the DAG. If, for example, I insert the following code > > Ops.push_back(Chain); > Chain = DAG.getNode(ISD::TRAP, DAG.getVTList(MVT::Other), &Ops[0], > Ops.size()); > > then an X86 instruction (namely ud2) appears in the output files > compiled by > llc. > So, is my understanding correct that > 1) the Chain determines the ordering of the nodes? Yes. > 2) the second parameter is a set of retur...

...version: // inc eax Ops.push_back(Chain); Ops.push_back(DAG.getRegister(X86::EAX, MVT::i32)); // rather without target register? Ops.push_back(DAG.getRegister(X86::EAX, MVT::i32)); Ops.push_back(DAG.getConstant(1, MVT::i32)); Ops.push_back(InFlag); Chain = DAG.getNode(ISD::ADDC, DAG.getVTList(MVT::Other, MVT::Flag), &Ops[0], Ops.size()); InFlag = Chain.getValue(1); Usually, llc quits with the error message llc: SelectionDAG.cpp:4417: llvm::SDValue llvm::SelectionDAG::UpdateNodeOperands(llvm::SDValue, llvm::SDValue, llvm::SDValue): Assertion `N->getNumOperands() == 2 &&...

On Jun 26, 2009, at 4:49 AM, Artjom K. wrote: > > Thank you for your help. > > I think I managed to create the instruction I wanted: > > // mov eax, 41 > Chain = DAG.getCopyToReg(Chain, DAG.getRegister(X86::EAX, MVT::i32), > DAG.getConstant(41, MVT::i32), InFlag); > InFlag = Chain.getValue(1); > > I don't understand though what InFlag is for. As I read the

...unsigned MULHXOpcode = Opc == ISD::UMUL_LOHI ? ISD::MULHU : ISD::MULHS; SDValue res[2] = { // Seems wasteful to generate both of these twice per node DAG.getNode(ISD::MUL, dl, VT, Op0, Op1), LowerMULHX(DAG.getNode(MULHXOpcode, dl, VT, Op0, Op1), DAG), }; SDVTList VTs = DAG.getVTList(VT, VT); SDNode * N = DAG.getNode(ISD::MERGE_VALUES, dl, VTs, res[0], res[1]).getNode(); return SDValue(N,Op.getResNo()); // AArch64 doesn’t do this } The above is weird in at least two respects. It generates an ISD::MUL when ResNo == 1, which will then be dropped elsewhere, and likewi...

...ding nothing in &Results. The problem is that the Chain of the va_arg node needs to be updated but I dont know how to do that. I tried stuff like: SDValue Ops[] = { InChain, VAListPtr, N->getOperand(2), N->getOperand(3) }; SDValue NewNode = DAG.getNode(ISD::VAARG, dl, DAG.getVTList(VT, MVT::Other), Ops, 4); DAG.ReplaceAllUsesWith(N, NewNode.getNode()); // or this variant //DAG.ReplaceAllUsesWith(SDValue(N, 1), NewNode); but that does not work for various reasons (N having more than one value in the first case and N operand 2 not having legal type (i64))....

PPCTargetLowering::EmitInstrWithCustomInserter has a reference to the current MachineFunction for other purposes. Can you use MachineFunction::getRegInfo instead? Dan On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > Would it be acceptable to change MachineInstr::getRegInfo from private > to public so I can use it from > PPCTargetLowering::EmitInstrWithCustomInserter? > >

Just cast both values to const TargetRegisterClass*. Evan On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > Evan Cheng wrote: >> How about? >> >> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : >> &PPC:G8RCRegClass; >> unsigned TmpReg = RegInfo.createVirtualRegister(RC); > > I tried something like that yesterday: > > const

Evan Cheng wrote: > How about? > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > &PPC:G8RCRegClass; > unsigned TmpReg = RegInfo.createVirtualRegister(RC); I tried something like that yesterday: const TargetRegisterClass *RC = is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass; but I kept getting this error no matter how I arranged it:

You need to insert new basic blocks and update CFG to accomplish this. There is a hackish way to do this right now. Add a pseudo instruction to represent this operation and mark it usesCustomDAGSchedInserter. This means the intrinsic is mapped to a single (pseudo) node. But it is then expanded into instructions that can span multiple basic blocks. See

...erand Ptr = Op.getOperand(1); SDOperand Incr = Op.getOperand(2); - // Issue a "load and reserve". - std::vector<MVT> VTs; - VTs.push_back(VT); - VTs.push_back(MVT::Other); - - SDOperand Label = DAG.getConstant(PPCAtomicLabelIndex++, MVT::i32); + SDVTList VTs = DAG.getVTList(VT, MVT::Other); SDOperand Ops[] = { - Chain, // Chain - Ptr, // Ptr - Label, // Label + Chain, + Ptr, + Incr, }; - SDOperand Load = DAG.getNode(PPCISD::LARX, VTs, Ops, 3); - Chain = Load.getValue(1); - - // Compute new value. -...

Would it be acceptable to change MachineInstr::getRegInfo from private to public so I can use it from PPCTargetLowering::EmitInstrWithCustomInserter? Cheers, Gary Evan Cheng wrote: > Look for createVirtualRegister. These are examples in > PPCISelLowering.cpp. > > Evan > On Jul 8, 2008, at 8:24 AM, Gary Benson wrote: > > > Hi Evan, > > > > Evan Cheng wrote:

Chris Lattner wrote: > On Jun 27, 2008, at 8:27 AM, Gary Benson wrote: > > def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm: > > $label), > > "cmpw $rA, $rB\n\tbne- La${label}_exit", > > [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm: > > $label)]>; > > } > > > > ...and

...erand Ptr = Op.getOperand(1); SDOperand Incr = Op.getOperand(2); - // Issue a "load and reserve". - std::vector<MVT> VTs; - VTs.push_back(VT); - VTs.push_back(MVT::Other); - - SDOperand Label = DAG.getConstant(PPCAtomicLabelIndex++, MVT::i32); + SDVTList VTs = DAG.getVTList(VT, MVT::Other); SDOperand Ops[] = { - Chain, // Chain - Ptr, // Ptr - Label, // Label + Chain, + Ptr, + Incr, }; - SDOperand Load = DAG.getNode(PPCISD::LARX, VTs, Ops, 3); - Chain = Load.getValue(1); - - // Compute new value. -...

...thing then you completely sidestep DAG nodes at -O0. - Devang > > 02367 /// getNode - Gets or creates the specified node. > 02368 /// > 02369 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT) { > 02370 FoldingSetNodeID ID; > 02371 AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0); > 02372 void *IP = 0; > 02373 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) > 02374 return SDValue(E, 0); > 02375 > 02376 SDNode *N = new (NodeAllocator) SDNode(Opcode, DL, getVTList(VT)); > 02377 CSEMap.InsertNode(N, IP); > 02378 > 02379 Al...