search for: getvt

Displaying 3 results from an estimated 3 matches for "getvt".

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2011 Nov 03
3
[LLVMdev] Tablegen: Instructions that take immediates or registers as operands
..._imm). I have tried a few different ways to make this work in tablegen, but I have been unsuccessful so far. Here is an example of something I have tried. It fails to compile with tablegen, but I hope it can help demonstrate what I am trying to do: def F32Node : PatLeaf<(vt), [{return N->getVT() == MVT::f32;}]>; def F32Op : Operand <f32> { let MIOperandInfo = (ops GPR, f32imm); } def ADD : InstAMD < (outs GPR:$dst), (ins F32Op:$src0, F32Op:$src1), "ADD $dst, $src0, $src1"), [(set GPR:$dst, (fadd F32Node:$src0, F32Node:$sr...
2017 Jul 18
2
get ty2
Hello, in some operations there is a ty2 type, for example in truncate. What is the most right way to get it ? I have seen some EVT types, but this is connected to DAG... and I don't believe that there is no easy way to get ty2 with one call function. -------------- next part -------------- An HTML attachment was scrubbed... URL:
2011 Nov 03
0
[LLVMdev] Tablegen: Instructions that take immediates or registers as operands
...ferent ways to make this work in tablegen, but I > have been unsuccessful so far. Here is an example of something I have > tried. It fails to compile with tablegen, but I hope it can help > demonstrate what I am trying to do: > > > def F32Node : PatLeaf<(vt), [{return N->getVT() == MVT::f32;}]>; > > def F32Op : Operand <f32> { > let MIOperandInfo = (ops GPR, f32imm); > } > > def ADD : InstAMD < > (outs GPR:$dst), > (ins F32Op:$src0, F32Op:$src1), > "ADD $dst, $src0, $src1"), >...