search for: getvregdef

...%vreg85 dbg:IfVectorize.c:42:18 from BB#12 to BB#11 Can't remat / high reg-pressure: %vreg94<def> = COPY %vreg86; BoolMask:%vreg94 MSA128D:%vreg86 dbg:IfVectorize.c:42:13 llc: /llvm/lib/CodeGen/MachineRegisterInfo.cpp:339: llvm::MachineInstr* llvm::MachineRegisterInfo::getVRegDef(unsigned int) const: Assertion `(I.atEnd() || std::next(I) == def_instr_end()) && "getVRegDef assumes a single definition or no definition"' failed. 0 libLLVMSupport.so 0x00007f634e255700 llvm::sys::PrintStackTrace(llvm::raw_ostream&) + 72 1 libLLVMSupport....

...g with creating instructions that write into virtual registers that use the ARM GPRPair register class in Pre-RA phase. During register allocation, I hit an assertion because the code is not in SSA form: lib/CodeGen/MachineRegisterInfo.cpp:271: llvm::MachineInstr* llvm::MachineRegisterInfo::getVRegDef(unsigned int) const: Assertion `(I.atEnd() || llvm::next(I) == def_end()) && "getVRegDef assumes a single definition or no definition"' failed. The code in lib\CodeGen\MachineRegisterInfo.cpp has information about the virtual register's sub-register been written, but t...

...B#1 %vreg5<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg5 %EAX<def> = COPY %vreg5; GR32:%vreg5 RETQ %EAX # End machine code for function main. clang: /home/pyknite/work/ollvm/obfuscator-llvm/lib/CodeGen/MachineRegisterInfo.cpp:305: llvm::MachineInstr *llvm::MachineRegisterInfo::getVRegDef(unsigned int) const: Assertion `(I.atEnd() || std::next(I) == def_instr_end()) && "getVRegDef assumes a single definition or no definition"' failed. 0 clang 0x00000000027c3645 llvm::sys::PrintStackTrace(_IO_FILE*) + 37 1 clang 0x00000000027c3e33 2 libpthread.so.0 0x00007fba6de...

...ke to assign twice to the same physical register - but since I don't want to "mess" with the register allocator, I am using only virtual registers. However, if I write in my C++ code 2 getCopyToReg() calls to the same virtual register - this gives me the following error: "getVRegDef assumes a single definition or no definition" later, after instruction selection. Therefore, I try to use 2 virtual registers for the same physical register. I know in TablGen instruction specs we can give "tied-to" constraints on virtual registers of the form: string C...

Hi Matthias, Sorry for the late reply. Yes, you are correct, I do have optnone attribute on my function. I did pass -O0 to the tools. For your information, my invocations are as below: clang --target=mips-unknown-linux -mips32 test.c -emit-llvm -S llc -O0 -march=mips -mcpu=mips32 test.ll -o test.s Based on the generated .ll file, there is optnone attribute on the function, i

...ss:%7 416B MOV_A_ro @c1, def %8; FPUaOffsetClass:%8 Result: an assertion is raised... !! ********** PROCESS IMPLICIT DEFS ********** ********** Function: _start llc: /home/dte/eclipse-workspace/llvm/lib/CodeGen/MachineRegisterInfo.cpp:366: llvm::MachineInstr* llvm::MachineRegisterInfo::getVRegDef(unsigned int) const: Assertion `(I.atEnd() || std::next(I) == def_instr_end()) && "getVRegDef assumes a single definition or no definition"' failed. LLVMSymbolizer: error reading file: No such file or directory Here is the inner part of my customInserter. Are there any additi...

...<mbraun at apple.com> Cc: llvm-dev at lists.llvm.org Subject: Re: [llvm-dev] Live Register Spilling Sorry about the previous message This message showed up: llc: /home/jc/Desktop/Project/For_Testing/llvm/lib/CodeGen/MachineRegisterInfo.cpp:366: llvm::MachineInstr* llvm::MachineRegisterInfo::getVRegDef(unsigned int) const: Assertion `(I.atEnd() || std::next(I) == def_instr_end()) && "getVRegDef assumes a single definition or no definition"' failed. I am assuming that i messed up the virtual register allocation when i am using BuildMI(). Also, i cannot invoke the clang as...

Thanks Quentin. I'm trying to examine from the operands of the return instruction, and then to get the last assignment of those. I thought use_iterator/reg_iterator may suit better than just loop through the machine basicblock in the reverse order. Cheng-Chih On Thu, Sep 25, 2014 at 1:51 PM, Quentin Colombet <qcolombet at apple.com> wrote: > Hi Cheng-Chih, > > On Sep 25,

...fter changing the basic blocks, everything looks correct. But when the recompileAndRelinkFunction(Fn) is executed, I get the error: /home/varun/llvm-git/lib/CodeGen/MachineLICM.cpp:956: bool <anonymous namespace>::MachineLICM::IsLoopInvariantInst(llvm::MachineInstr &): Assertion `MRI->getVRegDef(Reg) && "Machine instr not mapped for this vreg?!"' failed. What am I missing? Thanks, Varun Agrawal

Hi, I am planning to expanding the pseudo instructions in XXXTargetLowering::EmitInstrWithCustomInserter(), and use temporary virtual registers as operands. If I use virtual registers, do I need to mark them as "early clobber"? I saw that sometimes they marked virtual register as "early clobber" in EmitInstrWithCustomInserter() in MIPS backend. What is the effect of marking a

Hello. Because I experience optimizations (DCE, OoO schedule) which mess the correct semantics of the list of instructions lowered in ISelLowering from the VSELECT LLVM instruction, and these bad transformations happen even before scheduling, at later I-sel subpasses, I try to fix this problem by lowering VSELECT to only one pseudo-instruction and LATER translate it to a list of

...t; Cc: llvm-dev at lists.llvm.org > Subject: Re: [llvm-dev] Live Register Spilling > > Sorry about the previous message > This message showed up: > llc: /home/jc/Desktop/Project/For_Testing/llvm/lib/CodeGen/MachineRegisterInfo.cpp:366: llvm::MachineInstr* llvm::MachineRegisterInfo::getVRegDef(unsigned int) const: Assertion `(I.atEnd() || std::next(I) == def_instr_end()) && "getVRegDef assumes a single definition or no definition"' failed. > I am assuming that i messed up the virtual register allocation when i am using BuildMI(). > > Also, i cannot invoke...

...=local -f aout.bc -o aout.s But fails with -tailcallopt with different error messages in each case: $ llc -O0 -tailcallopt -f aout.bc -o aout.s llc: LiveVariables.cpp:125: void llvm::LiveVariables::HandleVirtRegUse(unsigned int, llvm::MachineBasicBlock*, llvm::MachineInstr*): Assertion `MRI->getVRegDef(reg) && "Register use before def!"' failed. 0 llc 0x08b8efe8 Stack dump: 0. Program arguments: llc -O0 -tailcallopt -f aout.bc -o aout.s 1. Running pass 'Live Variable Analysis' on function '@"visit_array_aux<`Reference>"' Aborted...

On Sep 18, 2012, at 1:45 PM, Bjorn De Sutter <bjorn.desutter at elis.ugent.be> wrote: > I am working on a backend for a CGRA architecture with advanced predicate support (as on EPIC machines and as first used in the OpenIMPACT compiler). Until last month, the backend was working fine, but since the r161643 commit by stoklund, my backend doesn't work anymore. I think I noticed some

Hi, I am working on a backend for a CGRA architecture with advanced predicate support (as on EPIC machines and as first used in the OpenIMPACT compiler). Until last month, the backend was working fine, but since the r161643 commit by stoklund, my backend doesn't work anymore. I think I noticed some related commits later on, and the assertion I get on the latest trunk (r164162) differs from