Displaying 11 results from an estimated 11 matches for "getvectorvt".
2013 Aug 13
1
[LLVMdev] vector type legalization
...ements that is not a power of two are
always
- // widened, for example <3 x float> -> <4 x float>.
+ // widened, for example <3 x i8> -> <4 x i8>.
if (!VT.isPow2VectorType()) {
NumElts = (unsigned)NextPowerOf2(NumElts);
EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
+ while (!isTypeLegal(NVT)) {
+ NumElts = (unsigned)NextPowerOf2(NumElts);
+ NVT = EVT::getVectorVT(Context, EltVT, NumElts);
+ }
return LegalizeKind(TypeWidenVector, NVT);
}
From: llvmdev-bounces at cs.uiuc.edu [mailto:llv...
2013 Aug 13
0
[LLVMdev] vector type legalization
...r of two are always
> - // widened, for example <3 x float> -> <4 x float>.
> + // widened, for example <3 x i8> -> <4 x i8>.
> if (!VT.isPow2VectorType()) {
> NumElts = (unsigned)NextPowerOf2(NumElts);
> EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
> + while (!isTypeLegal(NVT)) {
> + NumElts = (unsigned)NextPowerOf2(NumElts);
> + NVT = EVT::getVectorVT(Context, EltVT, NumElts);
> + }
> return LegalizeKind(TypeWidenVector, NVT);
> }
>
>
Your pa...
2018 Apr 10
1
64 bit mask in x86vshuffle instruction
...= isShuffleEquivalent(V1, V2, Mask,
{0, 1, 2, 3, 4, 5, 6, 7,0, 1, 2, 3,
4, 5, 6, 7});
if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask,
{0, 1, 2, 3, 4, 5, 6, 7, 12, 13,
14, 15,16,17,18,19}))
{
MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(), 16);
SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
DAG.getIntPtrConstant(0, DL));
SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
OnlyUsesV1 ? V1 : V2,...
2018 Jan 29
0
Llvm support for non-power-of-2-sized vectors
Hi,
My target can support non-power-of-2-sized vectors. My first thought is to add the non-power-of-2 vector type to the function MVT::getVectorVT in MachineValueType.h, is this the correct approach?
I see code that checks for isPowOf2 for vectors in
lib<https://github.com/llvm-mirror/llvm/tree/master/lib>/CodeGen<https://github.com/llvm-mirror/llvm/tree/master/lib/CodeGen>/TargetLoweringBase.cpp
// FIXME: We don't support...
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
> Can you explain why you chose the approach of using a new pass?
> I pictured removing LegalizeDAG's type legalization code would
> mostly consist of finding all the places that use TLI.getTypeAction
> and just deleting code for handling its Expand and Promote. Are you
> anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote:
> On Wed, May 20, 2009 at 1:19 PM, Eli Friedman
> <eli.friedman at gmail.com> wrote:
>
>> Per subject, this patch adding an additional pass to handle vector
>>
>> operations; the idea is that this allows removing the code from
>>
>> LegalizeDAG that handles illegal types, which should be a significant
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...mElems = InVal->getValueType(InIx).getVectorNumElements();
- MVT EVT = InVal->getValueType(InIx).getVectorElementType();
-
- // Figure out if there is a simple type corresponding to this Vector
- // type. If so, convert to the vector type.
- MVT TVT = MVT::getVectorVT(EVT, NumElems);
- if (TLI.isTypeLegal(TVT)) {
- // Turn this into a return of the vector type.
- Tmp2 = LegalizeOp(Tmp2);
- Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
- } else if (NumElems == 1) {
- // Turn this into a re...
2016 Apr 29
3
Assert in TargetLoweringBase.cpp
This post is related to the following post
http://lists.llvm.org/pipermail/llvm-dev/2016-April/098823.html
I'm still trying to compile a library with clang. But now I'm getting as
assert in
lib/CodeGen/TargetLoweringBase.cpp:1155: virtual llvm::EVT
llvm::TargetLoweringBase::getSetCCResultType(llvm::LLVMContext&, llvm::EVT)
const: Assertion `!VT.isVector() && "No default
2016 Mar 28
0
RFC: atomic operations on SI+
...ing::LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const
> +{
> + SDLoc DL(Op);
> +
> + AtomicSDNode *Swap = cast<AtomicSDNode>(Op);
> + assert(Swap && Swap->isCompareAndSwap());
> +
> + EVT MemVT = Swap->getMemoryVT();
> + EVT ValVT = EVT::getVectorVT(*DAG.getContext(), MemVT, 2);
> + SDValue Cmp = Op.getOperand(2);
> + SDValue New = Op.getOperand(3);
> +
> + // "src comes from the first data-vgpr, cmp from the second."
> + SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, DL, ValVT, New, Cmp);
> +
> + SDValue Ops[...
2016 Mar 25
2
RFC: atomic operations on SI+
Hi Tom, Matt,
I'm working on a project that needs few coherent atomic operations (HSA
mode: load, store, compare-and-swap) for std::atomic_uint in HCC.
the attached patch implements atomic compare and swap for SI+
(untested). I tried to stay within what was available, but there are
few issues that I was unsure how to address:
1.) it currently uses v2i32 for both input and output. This
2016 Nov 04
2
[RFC] Supporting ARM's SVE in LLVM
...gt;` and `<n x 8 x i16>` have the same number of bytes.
## SelectionDAG
New scalable vector MVTs are added, one for each existing vector type. Scalable
vector MVTs are modelled in the same way as the IR. Hence, `<n x 4 x i32>`
becomes `nxv4i32`.
## MVT Interface:
```cpp
static MVT getVectorVT(MVT VT, ElementCount EC);
bool isScalableVector() const;
static mvt_range integer_scalable_valuetypes();
static mvt_range fp_scalable_valuetypes();
```
To minimise the effort required for common code to preserve the scalable flag
we extend the helper functions within MVT/EVT classes to cover...