search for: getvectornumelements

...llc -mattr=+avx ../../test/CodeGen/X86/widen_load-2.ll llc: LegalizeTypes.cpp:831: void llvm::DAGTypeLegalizer::SetSplitVector(llvm::SDValue, llvm::SDValue, llvm::SDValue): Assertion `Lo.getValueType().getVectorElementType() == Op.getValueType().getVectorElementType() && 2*Lo.getValueType().getVectorNumElements() == Op.getValueType().getVectorNumElements() && Hi.getValueType() == Lo.getValueType() && "Invalid type for split vector"' failed. The illegal CONCAT_VECTOR node is created from LegalizeVectorTypes.cpp DAGTypeLegalizer::GenWidenVectorLoads() I saw that this code com...

...pe ...>>>> as a <scalable I x <(J * K * L * ...) x type>> for everything but result type. We could have methods on Type that return the next level down vector type, the scalar type under the vector type nest (probably getScalarType), and the number of total scalar elements (getVectorNumElementsRecursive) assuming VL is the first valid non-zero integer: so <scalable I x <J x <K x <L x ... type ...>>>> returns I * J * K * L * ... We will probably want to cache the innermost scalar type and the number of total scalar elements. Since we want to avoid adding another fie...

...common to all targets and by introducing scalable vector MVTs they also apply to SVE as long as the "scalable" flag is preserved when transforming MVTs. To achieve this we want to popularise the use of functions like EVT::getHalfSizedIntegerVT as well as replace some common code uses of getVectorNumElements with another function that passes #Elements and the "scalable" flag as opaque data, using operator overloading when extending/shrinking #Elements proportionately. At the worst case, any common code that can never work for scalable vectors would be guarded by the "scalable" flag...

On Jan 6, 2012, at 5:08 PM, Chris Lattner wrote: >>> >>> It's very like SSA construction, but must make provision >>> testing anti dependences. I had planned to use dominance frontiers to >>> guide placement of phi nodes, as usual. >> >> Ok, in that case, please check out include/llvm/Transforms/Utils/SSAUpdater.h, >> which is the

...ter.cpp for Debug+Asserts build /home/rkotler/llvm_trunk/lib/Target/AArch64/AArch64ISelLowering.cpp:4244:22: error: comparison of integers of different signs: 'int' and 'unsigned int' [-Werror,-Wsign-compare] assert((Lane < V1.getOperand(0).getValueType().getVectorNumElements()) ~~~~ ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ /usr/include/assert.h:92:5: note: expanded from macro 'assert' ((expr) \ ^ make[3]: Entering directory `/home/rkotler/llvm/build/lib/Targe...

Jacob Lifshay <programmerjake at gmail.com> writes: > So it would be handy for the vector length on evl intrinsics to be in > units of the mask length so we don't have to pattern match a division > in the backend. We could have 2 variants of the vector length > argument, one in terms of the data vector and one in terms of the mask > vector. we could legalize the mask

...packed. And that elements larger than the byte size should be padded + // (e.g. i40 type for Phoenix is stored using 3 bytes (48 bits)). + bool PadElementsToByteSize = + isVector() && getScalarSizeInBits() >= BitsPerByte; + if (PadElementsToByteSize) + return getVectorNumElements() * getScalarType().getStoreSize(); + return (getSizeInBits() + (BitsPerByte-1)) / BitsPerByte; } The patch seems to work for in-tree-target tests as well as our out-of-tree target. If it is a correct assumption for all targets is beyond my knowledge. Maybe only i1 vectors should be bitp...

...build > /home/rkotler/llvm_trunk/lib/Target/AArch64/AArch64ISelLowering.cpp:4244:22: > error: > comparison of integers of different signs: 'int' and 'unsigned int' > [-Werror,-Wsign-compare] > assert((Lane < > V1.getOperand(0).getValueType().getVectorNumElements()) > ~~~~ ^ > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > /usr/include/assert.h:92:5: note: expanded from macro 'assert' > ((expr) \ > ^ > make[3]: Entering directory `/home/rk...

...; should be padded > > +      // (e.g. i40 type for Phoenix is stored using 3 bytes (48 bits)). > > +      bool PadElementsToByteSize = > > +        isVector() && getScalarSizeInBits() >= BitsPerByte; > > +      if (PadElementsToByteSize) > > +        return getVectorNumElements() * getScalarType().getStoreSize(); > > +      return (getSizeInBits() + (BitsPerByte-1)) / BitsPerByte; > >      } > > The patch seems to work for in-tree-target tests as well as our > out-of-tree target. > > If it is a correct assumption for all targets is beyond my kn...

...er/llvm_trunk/lib/Target/AArch64/AArch64ISelLowering.cpp:4244:22: >> error: >> comparison of integers of different signs: 'int' and 'unsigned int' >> [-Werror,-Wsign-compare] >> assert((Lane < >> V1.getOperand(0).getValueType().getVectorNumElements()) >> ~~~~ ^ >> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >> /usr/include/assert.h:92:5: note: expanded from macro 'assert' >> ((expr) \ >> ^ >> make[3]: E...

On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote: > Can you explain why you chose the approach of using a new pass? > I pictured removing LegalizeDAG's type legalization code would > mostly consist of finding all the places that use TLI.getTypeAction > and just deleting code for handling its Expand and Promote. Are you > anticipating something more

On May 20, 2009, at 1:34 PM, Eli Friedman wrote: > On Wed, May 20, 2009 at 1:19 PM, Eli Friedman > <eli.friedman at gmail.com> wrote: > >> Per subject, this patch adding an additional pass to handle vector >> >> operations; the idea is that this allows removing the code from >> >> LegalizeDAG that handles illegal types, which should be a significant

...FP(-0.0, Op.getValueType()); + return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), + Zero, Op.getOperand(0)); + } + return UnrollVectorOp(Op); +} + +SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) { + MVT VT = Op.getValueType(); + unsigned NumElems = VT.getVectorNumElements(); + MVT EltVT = VT.getVectorElementType(); + SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2); + MVT TmpEltVT = LHS.getValueType().getVectorElementType(); + DebugLoc dl = Op.getDebugLoc(); + SmallVector<SDValue, 8> Ops(NumElems); + for (unsigned i = 0; i &l...

...t;. LLVM is then changing it to be a 32bit type and it asserts in : getCopyToParts(DAG, SDValue(RetOp.getNode(), RetOp.getResNo() + j), &Parts[0], NumParts, PartVT, ExtendKind); Here: assert(ValueVT.getVectorElementType() == PartVT && ValueVT.getVectorNumElements() == 1 && "Only trivial vector-to-scalar conversions should get here!"); Because it switched PartVT from a vector type<2xi8> into a scalar integer<i32>. Any idea's on how I can get around this constraint? Thanks, Micah Villmow Systems Eng...

They are starting to look complicated. The patch linked is interesting, perhaps v1 vectors are special cased. It shouldn't be too onerous to work out what one or two in tree back ends do by experimentation. Thanks again, it's great to have context beyond the source. On Fri, Sep 15, 2017 at 9:41 PM, Friedman, Eli <efriedma at codeaurora.org> wrote: > On 9/15/2017 12:10 PM, Jon

..., i32 1 %4 = extractelement <4 x i1> %1, i32 2 %5 = extractelement <4 x i1> %1, i32 3 %6 = or i1 %2, %3 %7 = or i1 %4, %5 %8 = or i1 %6, %7 ret i1 %8 } This fails with: Assertion failed: (isVector() && "Invalid vector type!"), function getVectorNumElements, file /Users/cbasile/src/llvm-2.4/include/llvm/ CodeGen/ValueTypes.h, line 339. Approach 3 ---------------- define i1 @VectorCompare3(i128 %x, i128 %y) { %1 = icmp eq i128 %x, %y ret i1 %1 } This fails with: Cannot yet select: 0x10182b4: i8 = setcc 0x101844c, 0x10184d4, 0x100becc -...

...TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { ... isShuffleMaskLegal(...) } bool X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const { // FIXME: pshufb, blends, shifts. return (VT.getVectorNumElements() == 2 || ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isMOVLMask(M, VT) || isSHUFPMask(M, VT) || ... } We git rid of this call to isSHUFPMask, which currently happens during legalize. Instead of trying to see if shuffles are already legal, just run t...

...t the scalars +/// and operating on each element individually. +SDValue VectorLegalizer::UnrollVectorOp(SDValue Op) { + MVT VT = Op.getValueType(); + assert(Op.getNode()->getNumValues() == 1 && + "Can't unroll a vector with multiple results!"); + unsigned NE = VT.getVectorNumElements(); + MVT EltVT = VT.getVectorElementType(); + DebugLoc dl = Op.getDebugLoc(); + + SmallVector<SDValue, 8> Scalars; + SmallVector<SDValue, 4> Operands(Op.getNumOperands()); + for (unsigned i = 0; i != NE; ++i) { + for (unsigned j = 0; j != Op.getNumOperands(); ++j) { + SDVal...

...packed. And that elements larger than the byte size should be padded + // (e.g. i40 type for Phoenix is stored using 3 bytes (48 bits)). + bool PadElementsToByteSize = + isVector() && getScalarSizeInBits() >= BitsPerByte; + if (PadElementsToByteSize) + return getVectorNumElements() * getScalarType().getStoreSize(); + return (getSizeInBits() + (BitsPerByte-1)) / BitsPerByte; } The patch seems to work for in-tree-target tests as well as our out-of-tree target. If it is a correct assumption for all targets is beyond my knowledge. Maybe only i1 vectors should be bitp...

...would give us >> all of the problems we had before by moving to X86ISD nodes. > > bool X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, > EVT VT) const { > // FIXME: pshufb, blends, shifts. > return (VT.getVectorNumElements() == 2 || > ShuffleVectorSDNode::isSplatMask(&M[0], VT) || > isMOVLMask(M, VT) || > isSHUFPMask(M, VT) || > ... > } > > We git rid of this call to isSHUFPMask, which currently happens during > legalize. Instead of trying to see if sh...