search for: getvectorelementtyp

Hello Chris, We caught this failure: ./llc -mattr=+avx ../../test/CodeGen/X86/widen_load-2.ll llc: LegalizeTypes.cpp:831: void llvm::DAGTypeLegalizer::SetSplitVector(llvm::SDValue, llvm::SDValue, llvm::SDValue): Assertion `Lo.getValueType().getVectorElementType() == Op.getValueType().getVectorElementType() && 2*Lo.getValueType().getVectorNumElements() == Op.getValueType().getVectorNumElements() && Hi.getValueType() == Lo.getValueType() && "Invalid type for split vector"' failed. The illegal CONCAT_VECTOR node is cre...

On Jan 6, 2012, at 5:08 PM, Chris Lattner wrote: >>> >>> It's very like SSA construction, but must make provision >>> testing anti dependences. I had planned to use dominance frontiers to >>> guide placement of phi nodes, as usual. >> >> Ok, in that case, please check out include/llvm/Transforms/Utils/SSAUpdater.h, >> which is the

> so I think we need to use non-extending load for element size less than 8bit on "DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT" like this roughly. > if (N->getOperand(0).getValueType().getVectorElementType().getSizeInBits() < 8) { > return DAG.getLoad(N->getValueType(0), dl, Store, StackPtr, MachinePointerInfo()); > } else { > return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr, MachinePointerInfo(), EltVT); > } I assume that we need the opposite -...

...86TargetLowering::isCheapToSpeculateCtlz() > const { > > bool X86TargetLowering::isLoadBitCastBeneficial(EVT LoadVT, > EVT BitcastVT) const { > + if (!LoadVT.isVector() && BitcastVT.isVector() && > + BitcastVT.getVectorElementType() == MVT::i1 && > + !Subtarget.hasAVX512()) > + return false; > + > if (!Subtarget.hasDQI() && BitcastVT == MVT::v8i1) > return false; > > > ~Craig > > > On Mon, Nov 26, 2018 at 2:51 PM Johan Engelen via llvm-dev < > llvm-dev a...

...bitsLT(VT.getScalarType()) && "Should only be an extending load, not truncating!") so I think we need to use non-extending load for element size less than 8bit on "DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT" like this roughly. if (N->getOperand(0).getValueType().getVectorElementType().getSizeInBits() < 8) { return DAG.getLoad(N->getValueType(0), dl, Store, StackPtr, MachinePointerInfo()); } else { return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr, MachinePointerInfo(), EltVT); } How do you think about it? Thanks, JinGu Kang On 15/09/...

...tracking. Here is a reduced test case. Reproduce with llc -mattr=+Altivec -mcpu=g5. The backtrace looks like this: #0 0x9333ae42 in __kill () #1 0x9333ae34 in kill$UNIX2003 () #2 0x933ad23a in raise () #3 0x933b9679 in abort () #4 0x933ae3db in __assert_rtn () #5 0x0008bd8f in llvm::MVT::getVectorElementType (this=0xbfffdda4) at ValueTypes.h:317 #6 0x002aed06 in BuildSplatI (Val=0, SplatSize=8, VT={{V = 24, SimpleTy = llvm::MVT::v4i32, LLVMTy = 0x18}}, DAG=@0x16088a0, dl={Idx = 4294967295}) at PPCISelLowering.cpp:311\ 5 #7 0x002afae4 in llvm::PPCTargetLowering::LowerBUILD_VECTOR (this=0x1803...

...lement individually. +SDValue VectorLegalizer::UnrollVectorOp(SDValue Op) { + MVT VT = Op.getValueType(); + assert(Op.getNode()->getNumValues() == 1 && + "Can't unroll a vector with multiple results!"); + unsigned NE = VT.getVectorNumElements(); + MVT EltVT = VT.getVectorElementType(); + DebugLoc dl = Op.getDebugLoc(); + + SmallVector<SDValue, 8> Scalars; + SmallVector<SDValue, 4> Operands(Op.getNumOperands()); + for (unsigned i = 0; i != NE; ++i) { + for (unsigned j = 0; j != Op.getNumOperands(); ++j) { + SDValue Operand = Op.getOperand(j); + MVT...

On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote: > Can you explain why you chose the approach of using a new pass? > I pictured removing LegalizeDAG's type legalization code would > mostly consist of finding all the places that use TLI.getTypeAction > and just deleting code for handling its Expand and Promote. Are you > anticipating something more

On May 20, 2009, at 1:34 PM, Eli Friedman wrote: > On Wed, May 20, 2009 at 1:19 PM, Eli Friedman > <eli.friedman at gmail.com> wrote: > >> Per subject, this patch adding an additional pass to handle vector >> >> operations; the idea is that this allows removing the code from >> >> LegalizeDAG that handles illegal types, which should be a significant

Hi all, I've run into a case where the optimizer seems to be having trouble doing the "obvious" thing. Consider this code: ``` define i16 @foo(<8 x i16>* dereferenceable(16) %egress, <16 x i8> %a0) { %a1 = icmp slt <16 x i8> %a0, zeroinitializer %a2 = bitcast <16 x i1> %a1 to i16 %astore = getelementptr inbounds <8 x i16>, <8 x i16>*

...AG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), + Zero, Op.getOperand(0)); + } + return UnrollVectorOp(Op); +} + +SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) { + MVT VT = Op.getValueType(); + unsigned NumElems = VT.getVectorNumElements(); + MVT EltVT = VT.getVectorElementType(); + SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2); + MVT TmpEltVT = LHS.getValueType().getVectorElementType(); + DebugLoc dl = Op.getDebugLoc(); + SmallVector<SDValue, 8> Ops(NumElems); + for (unsigned i = 0; i < NumElems; ++i) { + SDValue LHSElem...

...valent(V1, V2, Mask, {0, 1, 2, 3, 4, 5, 6, 7,0, 1, 2, 3, 4, 5, 6, 7}); if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 2, 3, 4, 5, 6, 7, 12, 13, 14, 15,16,17,18,19})) { MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(), 16); SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1, DAG.getIntPtrConstant(0, DL)); SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, OnlyUsesV1 ? V1 : V2, DAG.getIntPtr...

.... Reproduce with llc -mattr=+Altivec -mcpu=g5. > The backtrace looks like this: > > #0 0x9333ae42 in __kill () > #1 0x9333ae34 in kill$UNIX2003 () > #2 0x933ad23a in raise () > #3 0x933b9679 in abort () > #4 0x933ae3db in __assert_rtn () > #5 0x0008bd8f in llvm::MVT::getVectorElementType (this=0xbfffdda4) > at ValueTypes.h:317 > #6 0x002aed06 in BuildSplatI (Val=0, SplatSize=8, VT={{V = 24, > SimpleTy = llvm::MVT::v4i32, LLVMTy = 0x18}}, DAG=@0x16088a0, > dl={Idx = 4294967295}) at PPCISelLowering.cpp:311\ > 5 > #7 0x002afae4 in llvm::PPCTargetLowering::Lo...

...-mattr=+Altivec -mcpu=g5. The >> backtrace looks like this: >> #0 0x9333ae42 in __kill () >> #1 0x9333ae34 in kill$UNIX2003 () >> #2 0x933ad23a in raise () >> #3 0x933b9679 in abort () >> #4 0x933ae3db in __assert_rtn () >> #5 0x0008bd8f in llvm::MVT::getVectorElementType (this=0xbfffdda4) at >> ValueTypes.h:317 >> #6 0x002aed06 in BuildSplatI (Val=0, SplatSize=8, VT={{V = 24, SimpleTy = >> llvm::MVT::v4i32, LLVMTy = 0x18}}, DAG=@0x16088a0, dl={Idx = 4294967295}) at >> PPCISelLowering.cpp:311\ >> 5 >> #7 0x002afae4 in llvm::PPC...

...lement individually. +SDValue VectorLegalizer::UnrollVectorOp(SDValue Op) { + MVT VT = Op.getValueType(); + assert(Op.getNode()->getNumValues() == 1 && + "Can't unroll a vector with multiple results!"); + unsigned NE = VT.getVectorNumElements(); + MVT EltVT = VT.getVectorElementType(); + DebugLoc dl = Op.getDebugLoc(); + + SmallVector<SDValue, 8> Scalars; + SmallVector<SDValue, 4> Operands(Op.getNumOperands()); + for (unsigned i = 0; i != NE; ++i) { + for (unsigned j = 0; j != Op.getNumOperands(); ++j) { + SDValue Operand = Op.getOperand(j); + MVT...

...st case. Reproduce with llc -mattr=+Altivec -mcpu=g5. The > backtrace looks like this: > #0 0x9333ae42 in __kill () > #1 0x9333ae34 in kill$UNIX2003 () > #2 0x933ad23a in raise () > #3 0x933b9679 in abort () > #4 0x933ae3db in __assert_rtn () > #5 0x0008bd8f in llvm::MVT::getVectorElementType (this=0xbfffdda4) at > ValueTypes.h:317 > #6 0x002aed06 in BuildSplatI (Val=0, SplatSize=8, VT={{V = 24, SimpleTy = > llvm::MVT::v4i32, LLVMTy = 0x18}}, DAG=@0x16088a0, dl={Idx = 4294967295}) at > PPCISelLowering.cpp:311\ > 5 > #7 0x002afae4 in llvm::PPCTargetLowering::LowerBUI...

...} This is occurring when VT is a 16bit vector type,<2x i8>. LLVM is then changing it to be a 32bit type and it asserts in : getCopyToParts(DAG, SDValue(RetOp.getNode(), RetOp.getResNo() + j), &Parts[0], NumParts, PartVT, ExtendKind); Here: assert(ValueVT.getVectorElementType() == PartVT && ValueVT.getVectorNumElements() == 1 && "Only trivial vector-to-scalar conversions should get here!"); Because it switched PartVT from a vector type<2xi8> into a scalar integer<i32>. Any idea's on how I...

Got it. Thanks. I will try it with the trunk version. On Wed, Jan 20, 2016 at 1:36 PM, Tim Northover <t.p.northover at gmail.com> wrote: > Hi Zhi, > On 20 January 2016 at 13:33, zhi chen <zchenhn at gmail.com> wrote: > > Thanks for your response. The attached is the .bc file after my pass. I > > could generate the assembly with -mcpu=skx but not with

> extends the elements to 8bit and stores them on stack. Store is responsible for zero-extend. This is the policy... - Elena -----Original Message----- From: jingu at codeplay.com [mailto:jingu at codeplay.com] Sent: Friday, September 15, 2017 17:45 To: llvm-dev at lists.llvm.org; Demikhovsky, Elena <elena.demikhovsky at intel.com>; daniel_l_sanders at apple.com Subject: Re: Question

...ivec - >> mcpu=g5. The backtrace looks like this: >> >> #0 0x9333ae42 in __kill () >> #1 0x9333ae34 in kill$UNIX2003 () >> #2 0x933ad23a in raise () >> #3 0x933b9679 in abort () >> #4 0x933ae3db in __assert_rtn () >> #5 0x0008bd8f in llvm::MVT::getVectorElementType (this=0xbfffdda4) >> at ValueTypes.h:317 >> #6 0x002aed06 in BuildSplatI (Val=0, SplatSize=8, VT={{V = 24, >> SimpleTy = llvm::MVT::v4i32, LLVMTy = 0x18}}, DAG=@0x16088a0, >> dl={Idx = 4294967295}) at PPCISelLowering.cpp:311\ >> 5 >> #7 0x002afae4 in llv...