search for: getvaluetype

On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote: > Can you explain why you chose the approach of using a new pass? > I pictured removing LegalizeDAG's type legalization code would > mostly consist of finding all the places that use TLI.getTypeAction > and just deleting code for handling its Expand and Promote. Are you > anticipating something more

On May 20, 2009, at 1:34 PM, Eli Friedman wrote: > On Wed, May 20, 2009 at 1:19 PM, Eli Friedman > <eli.friedman at gmail.com> wrote: > >> Per subject, this patch adding an additional pass to handle vector >> >> operations; the idea is that this allows removing the code from >> >> LegalizeDAG that handles illegal types, which should be a significant

...TargetLowering::BuildFILD(SDValue Op, MVT SrcVT, SDValue Chain, + SDValue StackSlot, + SelectionDAG &DAG) { // Build the FILD + DebugLoc dl = Op.getDebugLoc(); SDVTList Tys; bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); if (useSSE) @@ -4792,36 +4802,54 @@ return SDValue(); return LowerUINT_TO_FP_i64(Op, DAG); - } else if (SrcVT == MVT::i32) { + } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) { return LowerUINT_TO_FP_i32(Op, DAG); } - assert(0 && "Unknown UINT...

...ne how conversion functions are lowered? In SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) ... case ISD::SINT_TO_FP: case ISD::UINT_TO_FP: case ISD::EXTRACT_VECTOR_ELT: Action = TLI.getOperationAction(Node->getOpcode(), Node->getOperand(0).getValueType()); This seems incorrect as SINT_TO_FP should be querying the convert action, and not the Operation action. i.e. it should be: case ISD::SINT_TO_FP: case ISD::UINT_TO_FP: case ISD::FP_TO_SINT: case ISD::FP_TO_UINT: Action = TLI.getConvertAction(Node->getValueType(),...

...? void DAGTypeLegalizer::SplitVecRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) { SDValue LHSLo, LHSHi; GetSplitVector(N->getOperand(0), LHSLo, LHSHi); DebugLoc dl = N->getDebugLoc(); EVT LoVT, HiVT; GetSplitDestVTs(N->getValueType(1), LoVT, HiVT); Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, DAG.getValueType(LoVT)); Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, DAG.getValueType(HiVT)); } Thanks, Micah > -----Original Message----- > From: llvmdev-bounces at cs.uiuc....

Hello Chris, We caught this failure: ./llc -mattr=+avx ../../test/CodeGen/X86/widen_load-2.ll llc: LegalizeTypes.cpp:831: void llvm::DAGTypeLegalizer::SetSplitVector(llvm::SDValue, llvm::SDValue, llvm::SDValue): Assertion `Lo.getValueType().getVectorElementType() == Op.getValueType().getVectorElementType() && 2*Lo.getValueType().getVectorNumElements() == Op.getValueType().getVectorNumElements() && Hi.getValueType() == Lo.getValueType() && "Invalid type for split vector"' failed. The illegal CON...

Anyone else ever get Value::getValueType and SDNode::getValueType confused? They're very different things. Could I suggest a renaming of Value::getValueType to getValueID? Dan -- Dan Gohman, Cray Inc.

...es_SIGN_EXTEND_INREG(SDNode *N, SDValue > &Lo, > SDValue &Hi) { > SDValue LHSLo, LHSHi; > GetSplitVector(N->getOperand(0), LHSLo, LHSHi); > DebugLoc dl = N->getDebugLoc(); > EVT LoVT, HiVT; > GetSplitDestVTs(N->getValueType(1), LoVT, HiVT); > > Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, > DAG.getValueType(LoVT)); > Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, > DAG.getValueType(HiVT)); > } > > > Thanks, > Micah > > -----Origin...

...> In SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) > > ... > case ISD::SINT_TO_FP: > case ISD::UINT_TO_FP: > case ISD::EXTRACT_VECTOR_ELT: > Action = TLI.getOperationAction(Node->getOpcode(), > Node->getOperand(0).getValueType()); > > This seems incorrect as SINT_TO_FP should be querying the convert action, and not the Operation action. > > i.e. it should be: > case ISD::SINT_TO_FP: > case ISD::UINT_TO_FP: > case ISD::FP_TO_SINT: > case ISD::FP_TO_UINT: > Action = TLI.getConvert...

After more digging, it seems that the SIGN_EXTEND_INREG is getting generated in DAGCombiner.cpp:3033. // fold (sext (truncate x)) -> (sextinreg x). if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType())) { if (Op.getValueType().bitsLT(VT)) Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); else if (Op.getValueType().bitsGT(VT)) Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT...

FAIL: /usr/home/llvm/obj/../test/Regression/CodeGen/X86/io.llx: Assertion failed: (ResNo < Values.size() && "Illegal result number!"), function getValueType, file /usr/home/llvm/obj/../include/llvm/CodeGen/SelectionDAGNodes.h, line 507. Abort trap (core dumped) FAIL: /usr/home/llvm/obj/../test/Regression/CodeGen/X86/ioport.llx: Assertion failed: (ResNo < Values.size() && "Illegal result number!"), function getValueType, file /u...

...its: (MACRO_FMA_f32:f32 GPRF32:f32:$src0, GPRF32:f32:$src1, GPRF32:f32:$src2) // Pattern complexity = 8 cost = 1 size = 0 if (CN1 == INT64_C(103)) { SDValue N2 = N.getOperand(2); SDValue N3 = N.getOperand(3); SDValue N4 = N.getOperand(4); if (N2.getNode()->getValueType(0) == MVT::f32 && N3.getNode()->getValueType(0) == MVT::f32 && N4.getNode()->getValueType(0) == MVT::f32) { SDNode *Result = Emit_28(N, AMDIL::MACRO_FMA_f32, MVT::f32); return Result; } } However, when MACRO_FMA is called...

...I have some doubt in LLVM Type Legalizer. How will LOAD:i8 with an i16 operand be lowered in type legalizer? (i16 type is not legal for our target) Following assertion in function ExpandIntegerOperand (file LegalizeIntegerTypes.cpp) is not allowing us to change LOAD node. assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && "Invalid operand expansion"); LOAD node has two values but the assertion checks N->getNumValues() == 1 which is not letting us change load operation. Also in the first check of the insertion, 0th value...

...he LHS side to work correctly, but then it fails instruction selection because of Other. I have not been able to figure out how to split the MVT::Other node yet, any idea how to do this? You should be able to split the contained type with GetSplitDestVTs, then recreate the node using SelectionDAG::getValueType(), I think. That said, it could possibly be considered a bug in DAGCombine that the second operand is a vector type; someone want to comment on that? -Eli

...n. The generic implementation is this: > > // Splat the sign bit into the register > SDValue SGN = > DAG.getNode(ISD::SRA, DL, VT, N0, > DAG.getConstant(VT.getScalarSizeInBits() - 1, DL, > getShiftAmountTy(N0.getValueType()))); > AddToWorklist(SGN.getNode()); > > // Add (N0 < 0) ? abs2 - 1 : 0; > SDValue SRL = > DAG.getNode(ISD::SRL, DL, VT, SGN, > DAG.getConstant(VT.getScalarSizeInBits() - lg2, DL, > getShiftAmountT...

...but then it fails instruction selection because of Other. I > have not been able to figure out how to split the MVT::Other node yet, > any idea how to do this? > > > You should be able to split the contained type with GetSplitDestVTs, > then recreate the node using SelectionDAG::getValueType(), I think. > > That said, it could possibly be considered a bug in DAGCombine that > the second operand is a vector type; someone want to comment on that? > > -Eli

I am getting an assert on a bad legalization. Assertion failed: Result.getValueType() == Op.getValueType() && "Bad legalization!", file ..\..\lib\CodeGen\SelectionDAG\LegalizeDAG.cpp, line 3976 Can someone explain to me what this means in term of backend code generation, how it might be occurring, and possible ways to fix this? I don't see how the value t...

On Mon, 2008-08-18 at 08:50 -0700, Eli Friedman wrote: > On Mon, Aug 18, 2008 at 6:31 AM, <Sachin.Punyani at microchip.com> wrote: > > assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && > > "Invalid operand expansion"); > > > > LOAD node has two values but the assertion checks N->getNumValues() == 1 > > which is not letting us change load operation. > Besides the ass...

Hi, The attached patch implements sub.ovf/mul.ovf intrinsics similarly to the recently added add.ovf intrinsics. These are useful for implementing some vm instructions like sub.ovf/mul.ovf in .NET IL efficiently. sub.ovf is supported in target independent lowering and on x86, while mul.ovf is only supported in the x86 backend. Please review

On Jan 6, 2012, at 5:08 PM, Chris Lattner wrote: >>> >>> It's very like SSA construction, but must make provision >>> testing anti dependences. I had planned to use dominance frontiers to >>> guide placement of phi nodes, as usual. >> >> Ok, in that case, please check out include/llvm/Transforms/Utils/SSAUpdater.h, >> which is the