Displaying 11 results from an estimated 11 matches for "getundef".
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gefunden
2018 Apr 10
1
64 bit mask in x86vshuffle instruction
...VectorElementType(), 2);
SDValue Subvec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
DAG.getIntPtrConstant(0, DL));
return insert128BitVector(V1, Subvec, V2Index * 2, DAG, DL);
}
// Try to lower to to vshuf64x2/vshuf32x4.
SDValue Ops[8] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT), DAG.getUNDEF(VT),
DAG.getUNDEF(VT), DAG.getUNDEF(VT), DAG.getUNDEF(VT), DAG.getUNDEF(VT),
DAG.getUNDEF(VT)};
unsigned PermMask = 0;
// Insure elements came from the same Op.
for (int i = 0; i < 16; ++i) {
assert(WidenedMask[i] >= -1);
if (WidenedMask[i] &l...
2009 Aug 21
2
[LLVMdev] Possible Typo in SelectionDAGLowering::visitShuffleVector
...ctionDAGBuild.cpp (revision
79629)
+++ F:/dev/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (working
copy)
@@ -2522,7 +2522,7 @@
}
}
- if (RangeUse[0] == 0 && RangeUse[0] == 0) {
+ if (RangeUse[0] == 0 && RangeUse[1] == 0) {
setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
return;
}
Marius Wachtler
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2020 Feb 07
2
Why does FPBinOp(X, undef) -> NaN?
...;re picking NaN for the value of the undef
operand since the result will always be a NaN.
So a few lines below this, we have something similar for integer operations:
case ISD::ADD:
case ISD::SUB:
case ISD::UDIV:
case ISD::SDIV:
case ISD::UREM:
case ISD::SREM:
return getUNDEF(VT); // fold op(arg1, undef) -> undef
What's the reasoning behind folding to undef here? Would that fall
into the same "any value can't produce some value" bin?
2016 Aug 23
2
Help in understanding physreg LiveVariables
So if I create a value with a DAG.getUndef(myVT); call during instruction
legalization, how can I access that value as input in another BB/DAG (also
during instruction legalization) without worrying about live-ins and/or phi
nodes?
Can I create a single virtual register and build both a CopyToReg and a
CopyFromReg node with it? I assumed t...
2016 Aug 23
2
Help in understanding physreg LiveVariables
...IBMUS
Cc: llvm-dev at lists.llvm.org
Date: 08/23/2016 05:17 PM
Subject: Re: [llvm-dev] Help in understanding physreg LiveVariables
Sent by: mbraun at apple.com
On Aug 23, 2016, at 2:07 PM, Tyler Kenney <tjkenney at us.ibm.com>
wrote:
So if I create a value with a DAG.getUndef(myVT); call during
instruction legalization, how can I access that value as input in
another BB/DAG (also during instruction legalization) without
worrying about live-ins and/or phi nodes?
Can I create a single virtual register and build both a CopyToReg and
a CopyFro...
2020 Feb 07
3
Why does FPBinOp(X, undef) -> NaN?
I came across this comment in SelectionDAG.cpp:
case ISD::FADD:
case ISD::FSUB:
case ISD::FMUL:
case ISD::FDIV:
case ISD::FREM:
// If both operands are undef, the result is undef. If 1 operand is undef,
// the result is NaN. This should match the behavior of the IR optimizer.
That isn't intuitive to me. I would have expected a binary FP
operation with one undef operand to
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
> Can you explain why you chose the approach of using a new pass?
> I pictured removing LegalizeDAG's type legalization code would
> mostly consist of finding all the places that use TLI.getTypeAction
> and just deleting code for handling its Expand and Promote. Are you
> anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote:
> On Wed, May 20, 2009 at 1:19 PM, Eli Friedman
> <eli.friedman at gmail.com> wrote:
>
>> Per subject, this patch adding an additional pass to handle vector
>>
>> operations; the idea is that this allows removing the code from
>>
>> LegalizeDAG that handles illegal types, which should be a significant
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...t;CopyFromReg must be legal!");
- default:
-#ifndef NDEBUG
- cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
-#endif
- assert(0 && "Do not know how to promote this operator!");
- abort();
- case ISD::UNDEF:
- Result = DAG.getUNDEF(NVT);
- break;
- case ISD::Constant:
- if (VT != MVT::i1)
- Result = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Op);
- else
- Result = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Op);
- assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
-...
2012 Feb 10
1
[LLVMdev] Prevent DAG combiner from changing "store ConstFP, addr" to integer store
This code lives in DAGCombiner.cpp:
-------------
// Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
// NOTE: If the original store is volatile, this transform must not
increase
// the number of stores. For example, on x86-32 an f64 can be stored
in one
// processor operation but
2016 Aug 23
2
Help in understanding physreg LiveVariables
<div class="socmaildefaultfont" dir="ltr" style="font-family:Arial;font-size:10.5pt" ><div dir="ltr" style="font-family:Arial;font-size:10.5pt" ><div dir="ltr" >Matthias,</div>
<div dir="ltr" > </div>
<div dir="ltr" >Thanks for the response.</div>
<div